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[PULL,00/24] tcg patch queue

Message ID 20250216000109.2606518-1-richard.henderson@linaro.org (mailing list archive)
State New
Headers show

Pull-request

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215

Message

Richard Henderson Feb. 16, 2025, midnight UTC 
With a couple of linux-user and target/sparc patches thrown in for good measure.

r~


The following changes since commit 495de0fd82d8bb2d7035f82d9869cfeb48de2f9e:

  Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging (2025-02-14 08:19:05 -0500)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215

for you to fetch changes up to 2132751069134114814c7e1609e9cf644f077aad:

  target/sparc: fake UltraSPARC T1 PCR and PIC registers (2025-02-15 12:04:13 -0800)

----------------------------------------------------------------
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
tcg: Cleanups after disallowing 64-on-32
tcg: Introduce constraint for zero register
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
linux-user: Fix alignment when unmapping excess reservation
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
target/sparc: fake UltraSPARC T1 PCR and PIC registers

----------------------------------------------------------------
Andreas Schwab (1):
      linux-user: Move TARGET_SA_RESTORER out of generic/signal.h

Artyom Tarasenko (1):
      target/sparc: fake UltraSPARC T1 PCR and PIC registers

Fabiano Rosas (1):
      elfload: Fix alignment when unmapping excess reservation

Mikael Szreder (2):
      target/sparc: Fix register selection for all F*TOx and FxTO* instructions
      target/sparc: Fix gdbstub incorrectly handling registers f32-f62

Richard Henderson (19):
      tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
      tcg: Remove TCG_OVERSIZED_GUEST
      tcg: Drop support for two address registers in gen_ldst
      tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
      tcg/arm: Drop addrhi from prepare_host_addr
      tcg/i386: Drop addrhi from prepare_host_addr
      tcg/mips: Drop addrhi from prepare_host_addr
      tcg/ppc: Drop addrhi from prepare_host_addr
      tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
      plugins: Fix qemu_plugin_read_memory_vaddr parameters
      accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
      include/exec: Change vaddr to uintptr_t
      include/exec: Use uintptr_t in CPUTLBEntry
      tcg: Introduce the 'z' constraint for a hardware zero register
      tcg/aarch64: Use 'z' constraint
      tcg/loongarch64: Use 'z' constraint
      tcg/mips: Use 'z' constraint
      tcg/riscv: Use 'z' constraint
      tcg/sparc64: Use 'z' constraint

 include/exec/tlb-common.h             |  10 +-
 include/exec/vaddr.h                  |  16 ++--
 include/qemu/atomic.h                 |  18 +---
 include/tcg/oversized-guest.h         |  23 -----
 include/tcg/tcg-opc.h                 |  28 ++----
 include/tcg/tcg.h                     |   3 +-
 linux-user/aarch64/target_signal.h    |   2 +
 linux-user/arm/target_signal.h        |   2 +
 linux-user/generic/signal.h           |   1 -
 linux-user/i386/target_signal.h       |   2 +
 linux-user/m68k/target_signal.h       |   1 +
 linux-user/microblaze/target_signal.h |   2 +
 linux-user/ppc/target_signal.h        |   2 +
 linux-user/s390x/target_signal.h      |   2 +
 linux-user/sh4/target_signal.h        |   2 +
 linux-user/x86_64/target_signal.h     |   2 +
 linux-user/xtensa/target_signal.h     |   2 +
 tcg/aarch64/tcg-target-con-set.h      |  12 +--
 tcg/aarch64/tcg-target.h              |   2 +
 tcg/loongarch64/tcg-target-con-set.h  |  15 ++-
 tcg/loongarch64/tcg-target-con-str.h  |   1 -
 tcg/loongarch64/tcg-target.h          |   2 +
 tcg/mips/tcg-target-con-set.h         |  26 +++---
 tcg/mips/tcg-target-con-str.h         |   1 -
 tcg/mips/tcg-target.h                 |   2 +
 tcg/riscv/tcg-target-con-set.h        |  10 +-
 tcg/riscv/tcg-target-con-str.h        |   1 -
 tcg/riscv/tcg-target.h                |   2 +
 tcg/sparc64/tcg-target-con-set.h      |  12 +--
 tcg/sparc64/tcg-target-con-str.h      |   1 -
 tcg/sparc64/tcg-target.h              |   3 +-
 tcg/tci/tcg-target.h                  |   1 -
 accel/tcg/cputlb.c                    |  32 ++-----
 accel/tcg/tcg-all.c                   |   9 +-
 linux-user/elfload.c                  |   4 +-
 plugins/api.c                         |   2 +-
 target/arm/ptw.c                      |  34 -------
 target/riscv/cpu_helper.c             |  13 +--
 target/sparc/gdbstub.c                |  18 +++-
 target/sparc/translate.c              |  19 ++++
 tcg/optimize.c                        |  21 ++---
 tcg/tcg-op-ldst.c                     | 103 +++++----------------
 tcg/tcg.c                             |  97 +++++++++----------
 tcg/tci.c                             | 119 +++++-------------------
 docs/devel/multi-thread-tcg.rst       |   1 -
 docs/devel/tcg-ops.rst                |   4 +-
 target/sparc/insns.decode             |  19 ++--
 tcg/aarch64/tcg-target.c.inc          |  86 +++++++----------
 tcg/arm/tcg-target.c.inc              | 104 ++++++---------------
 tcg/i386/tcg-target.c.inc             | 125 +++++++------------------
 tcg/loongarch64/tcg-target.c.inc      |  72 ++++++---------
 tcg/mips/tcg-target.c.inc             | 169 +++++++++++-----------------------
 tcg/ppc/tcg-target.c.inc              | 164 ++++++++-------------------------
 tcg/riscv/tcg-target.c.inc            |  56 +++++------
 tcg/s390x/tcg-target.c.inc            |  40 +++-----
 tcg/sparc64/tcg-target.c.inc          |  45 ++++-----
 tcg/tci/tcg-target.c.inc              |  60 +++---------
 57 files changed, 536 insertions(+), 1089 deletions(-)
 delete mode 100644 include/tcg/oversized-guest.h

Comments

Stefan Hajnoczi Feb. 17, 2025, 8:32 a.m. UTC | #1 
Please take a look at the following CI failure:
https://gitlab.com/qemu-project/qemu/-/jobs/9153630625#L5195

Thanks,
Stefan