| Message ID | 20250217071934.86131-2-adityag@linux.ibm.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Implement MPIPL for PowerNV | expand |
On 2/17/25 12:49, Aditya Gupta wrote: > During MPIPL (aka fadump), OPAL triggers the S0 SBE interrupt to trigger > MPIPL. > > Currently QEMU treats it as "Unimplemented", handle the interrupts by > just logging that the interrupt happened. > > Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> > --- > hw/ppc/pnv_sbe.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c > index 74cee4eea7ad..62c94a04a2df 100644 > --- a/hw/ppc/pnv_sbe.c > +++ b/hw/ppc/pnv_sbe.c > @@ -109,6 +109,19 @@ static void pnv_sbe_power9_xscom_ctrl_write(void *opaque, hwaddr addr, > trace_pnv_sbe_xscom_ctrl_write(addr, val); > > switch (offset) { > + case SBE_CONTROL_REG_RW: > + switch (val) { > + case SBE_CONTROL_REG_S0: > + qemu_log_mask(LOG_UNIMP, "SBE: S0 Interrupt triggered\n"); > + break; > + case SBE_CONTROL_REG_S1: > + qemu_log_mask(LOG_UNIMP, "SBE: S1 Interrupt triggered\n"); > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%" This log could be made specific to SBE unimplemented register "bits", otherwise fall back to outer switch-default case. > + HWADDR_PRIx "\n", addr >> 3); > + } > + break; > default: > qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%" > HWADDR_PRIx "\n", addr >> 3);
diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c index 74cee4eea7ad..62c94a04a2df 100644 --- a/hw/ppc/pnv_sbe.c +++ b/hw/ppc/pnv_sbe.c @@ -109,6 +109,19 @@ static void pnv_sbe_power9_xscom_ctrl_write(void *opaque, hwaddr addr, trace_pnv_sbe_xscom_ctrl_write(addr, val); switch (offset) { + case SBE_CONTROL_REG_RW: + switch (val) { + case SBE_CONTROL_REG_S0: + qemu_log_mask(LOG_UNIMP, "SBE: S0 Interrupt triggered\n"); + break; + case SBE_CONTROL_REG_S1: + qemu_log_mask(LOG_UNIMP, "SBE: S1 Interrupt triggered\n"); + break; + default: + qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%" + HWADDR_PRIx "\n", addr >> 3); + } + break; default: qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%" HWADDR_PRIx "\n", addr >> 3);
During MPIPL (aka fadump), OPAL triggers the S0 SBE interrupt to trigger MPIPL. Currently QEMU treats it as "Unimplemented", handle the interrupts by just logging that the interrupt happened. Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> --- hw/ppc/pnv_sbe.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)