| Message ID | 20250217112039.138650-1-wangyuquan1236@phytium.com.cn (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | docs/cxl: Add serial number for persistent-memdev | expand |
On Mon, 17 Feb 2025 19:20:39 +0800 Yuquan Wang <wangyuquan1236@phytium.com.cn> wrote: > Add serial number parameter in the cxl persistent examples. > > Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn> Looks good. I've queued it up on my gitlab staging tree, but Michael if you want to pick this one directly that's fine as well. I should be pushing out my gitlab tree shortly (bit of networking fun to deal with). > --- > docs/system/devices/cxl.rst | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst > index 882b036f5e..e307caf3f8 100644 > --- a/docs/system/devices/cxl.rst > +++ b/docs/system/devices/cxl.rst > @@ -308,7 +308,7 @@ A very simple setup with just one directly attached CXL Type 3 Persistent Memory > -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \ > -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ > -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ > - -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ > + -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0,sn=0x1 \ > -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G > > A very simple setup with just one directly attached CXL Type 3 Volatile Memory device:: > @@ -349,13 +349,13 @@ the CXL Type3 device directly attached (no switches).:: > -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ > -device pxb-cxl,bus_nr=222,bus=pcie.0,id=cxl.2 \ > -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ > - -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ > + -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0,sn=0x1 \ > -device cxl-rp,port=1,bus=cxl.1,id=root_port14,chassis=0,slot=3 \ > - -device cxl-type3,bus=root_port14,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1 \ > + -device cxl-type3,bus=root_port14,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1,sn=0x2 \ > -device cxl-rp,port=0,bus=cxl.2,id=root_port15,chassis=0,slot=5 \ > - -device cxl-type3,bus=root_port15,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2 \ > + -device cxl-type3,bus=root_port15,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2,sn=0x3 \ > -device cxl-rp,port=1,bus=cxl.2,id=root_port16,chassis=0,slot=6 \ > - -device cxl-type3,bus=root_port16,persistent-memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3 \ > + -device cxl-type3,bus=root_port16,persistent-memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3,sn=0x4 \ > -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.targets.1=cxl.2,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k > > An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: > @@ -375,13 +375,13 @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: > -device cxl-rp,port=1,bus=cxl.1,id=root_port1,chassis=0,slot=1 \ > -device cxl-upstream,bus=root_port0,id=us0 \ > -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 \ > - -device cxl-type3,bus=swport0,persistent-memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0 \ > + -device cxl-type3,bus=swport0,persistent-memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0,sn=0x1 \ > -device cxl-downstream,port=1,bus=us0,id=swport1,chassis=0,slot=5 \ > - -device cxl-type3,bus=swport1,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1 \ > + -device cxl-type3,bus=swport1,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1,sn=0x2 \ > -device cxl-downstream,port=2,bus=us0,id=swport2,chassis=0,slot=6 \ > - -device cxl-type3,bus=swport2,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2 \ > + -device cxl-type3,bus=swport2,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2,sn=0x3 \ > -device cxl-downstream,port=3,bus=us0,id=swport3,chassis=0,slot=7 \ > - -device cxl-type3,bus=swport3,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3 \ > + -device cxl-type3,bus=swport3,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3,sn=0x4 \ > -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k > > Deprecations
> > Looks good. I've queued it up on my gitlab staging tree, but > Michael if you want to pick this one directly that's fine as well. > > I should be pushing out my gitlab tree shortly (bit of networking > fun to deal with). > Hi, Jonathan About qemu side, I have another question: Could the qemu provide simulated RCH-RCD topology now? Yuquan 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.
On Fri, 21 Feb 2025 10:51:11 +0800 Yuquan Wang <wangyuquan1236@phytium.com.cn> wrote: > > > > Looks good. I've queued it up on my gitlab staging tree, but > > Michael if you want to pick this one directly that's fine as well. > > > > I should be pushing out my gitlab tree shortly (bit of networking > > fun to deal with). > > > Hi, Jonathan > > About qemu side, I have another question: Could the qemu provide simulated > RCH-RCD topology now? No. So far no one has worked on that that I'm aware of. Jonathan > > Yuquan > > > 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 > Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.
On Thu, Feb 20, 2025 at 04:12:13PM +0000, Jonathan Cameron wrote: > On Mon, 17 Feb 2025 19:20:39 +0800 > Yuquan Wang <wangyuquan1236@phytium.com.cn> wrote: > > > Add serial number parameter in the cxl persistent examples. > > > > Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn> > Looks good. I've queued it up on my gitlab staging tree, but > Michael if you want to pick this one directly that's fine as well. See no reason to, I was not even CC'd. > I should be pushing out my gitlab tree shortly (bit of networking > fun to deal with). > > > --- > > docs/system/devices/cxl.rst | 18 +++++++++--------- > > 1 file changed, 9 insertions(+), 9 deletions(-) > > > > diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst > > index 882b036f5e..e307caf3f8 100644 > > --- a/docs/system/devices/cxl.rst > > +++ b/docs/system/devices/cxl.rst > > @@ -308,7 +308,7 @@ A very simple setup with just one directly attached CXL Type 3 Persistent Memory > > -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \ > > -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ > > -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ > > - -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ > > + -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0,sn=0x1 \ > > -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G > > > > A very simple setup with just one directly attached CXL Type 3 Volatile Memory device:: > > @@ -349,13 +349,13 @@ the CXL Type3 device directly attached (no switches).:: > > -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ > > -device pxb-cxl,bus_nr=222,bus=pcie.0,id=cxl.2 \ > > -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ > > - -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ > > + -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0,sn=0x1 \ > > -device cxl-rp,port=1,bus=cxl.1,id=root_port14,chassis=0,slot=3 \ > > - -device cxl-type3,bus=root_port14,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1 \ > > + -device cxl-type3,bus=root_port14,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1,sn=0x2 \ > > -device cxl-rp,port=0,bus=cxl.2,id=root_port15,chassis=0,slot=5 \ > > - -device cxl-type3,bus=root_port15,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2 \ > > + -device cxl-type3,bus=root_port15,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2,sn=0x3 \ > > -device cxl-rp,port=1,bus=cxl.2,id=root_port16,chassis=0,slot=6 \ > > - -device cxl-type3,bus=root_port16,persistent-memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3 \ > > + -device cxl-type3,bus=root_port16,persistent-memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3,sn=0x4 \ > > -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.targets.1=cxl.2,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k > > > > An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: > > @@ -375,13 +375,13 @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: > > -device cxl-rp,port=1,bus=cxl.1,id=root_port1,chassis=0,slot=1 \ > > -device cxl-upstream,bus=root_port0,id=us0 \ > > -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 \ > > - -device cxl-type3,bus=swport0,persistent-memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0 \ > > + -device cxl-type3,bus=swport0,persistent-memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0,sn=0x1 \ > > -device cxl-downstream,port=1,bus=us0,id=swport1,chassis=0,slot=5 \ > > - -device cxl-type3,bus=swport1,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1 \ > > + -device cxl-type3,bus=swport1,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1,sn=0x2 \ > > -device cxl-downstream,port=2,bus=us0,id=swport2,chassis=0,slot=6 \ > > - -device cxl-type3,bus=swport2,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2 \ > > + -device cxl-type3,bus=swport2,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2,sn=0x3 \ > > -device cxl-downstream,port=3,bus=us0,id=swport3,chassis=0,slot=7 \ > > - -device cxl-type3,bus=swport3,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3 \ > > + -device cxl-type3,bus=swport3,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3,sn=0x4 \ > > -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k > > > > Deprecations
> > On Thu, Feb 20, 2025 at 04:12:13PM +0000, Jonathan Cameron wrote: > > On Mon, 17 Feb 2025 19:20:39 +0800 > > Yuquan Wang <wangyuquan1236@phytium.com.cn> wrote: > > > > > Add serial number parameter in the cxl persistent examples. > > > > > > Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn> > > Looks good. I've queued it up on my gitlab staging tree, but > > Michael if you want to pick this one directly that's fine as well. > > See no reason to, I was not even CC'd. Hi, Michael I'm sorry, this is my fault. I used "get_maintainer.pl" to check this patch's maintainers but it shows "No maintainers found, printing recent contributors". Yuquan > > > I should be pushing out my gitlab tree shortly (bit of networking > > fun to deal with). > > > > > --- > > > docs/system/devices/cxl.rst | 18 +++++++++--------- > > > 1 file changed, 9 insertions(+), 9 deletions(-) > > > > > > diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst > > > index 882b036f5e..e307caf3f8 100644 > > > --- a/docs/system/devices/cxl.rst > > > +++ b/docs/system/devices/cxl.rst > > > @@ -308,7 +308,7 @@ A very simple setup with just one directly attached CXL Type 3 Persistent Memory > > > -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \ > > > -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ > > > -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ > > > - -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ > > > + -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0,sn=0x1 \ > > > -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G > > > > > > A very simple setup with just one directly attached CXL Type 3 Volatile Memory device:: > > > @@ -349,13 +349,13 @@ the CXL Type3 device directly attached (no switches).:: > > > -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ > > > -device pxb-cxl,bus_nr=222,bus=pcie.0,id=cxl.2 \ > > > -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ > > > - -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ > > > + -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0,sn=0x1 \ > > > -device cxl-rp,port=1,bus=cxl.1,id=root_port14,chassis=0,slot=3 \ > > > - -device cxl-type3,bus=root_port14,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1 \ > > > + -device cxl-type3,bus=root_port14,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1,sn=0x2 \ > > > -device cxl-rp,port=0,bus=cxl.2,id=root_port15,chassis=0,slot=5 \ > > > - -device cxl-type3,bus=root_port15,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2 \ > > > + -device cxl-type3,bus=root_port15,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2,sn=0x3 \ > > > -device cxl-rp,port=1,bus=cxl.2,id=root_port16,chassis=0,slot=6 \ > > > - -device cxl-type3,bus=root_port16,persistent-memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3 \ > > > + -device cxl-type3,bus=root_port16,persistent-memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3,sn=0x4 \ > > > -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.targets.1=cxl.2,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k > > > > > > An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: > > > @@ -375,13 +375,13 @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: > > > -device cxl-rp,port=1,bus=cxl.1,id=root_port1,chassis=0,slot=1 \ > > > -device cxl-upstream,bus=root_port0,id=us0 \ > > > -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 \ > > > - -device cxl-type3,bus=swport0,persistent-memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0 \ > > > + -device cxl-type3,bus=swport0,persistent-memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0,sn=0x1 \ > > > -device cxl-downstream,port=1,bus=us0,id=swport1,chassis=0,slot=5 \ > > > - -device cxl-type3,bus=swport1,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1 \ > > > + -device cxl-type3,bus=swport1,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1,sn=0x2 \ > > > -device cxl-downstream,port=2,bus=us0,id=swport2,chassis=0,slot=6 \ > > > - -device cxl-type3,bus=swport2,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2 \ > > > + -device cxl-type3,bus=swport2,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2,sn=0x3 \ > > > -device cxl-downstream,port=3,bus=us0,id=swport3,chassis=0,slot=7 \ > > > - -device cxl-type3,bus=swport3,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3 \ > > > + -device cxl-type3,bus=swport3,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3,sn=0x4 \ > > > -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k > > > > > > Deprecations 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.
On Tue, 4 Mar 2025 14:22:48 +0800 Yuquan Wang <wangyuquan1236@phytium.com.cn> wrote: > > > > On Thu, Feb 20, 2025 at 04:12:13PM +0000, Jonathan Cameron wrote: > > > On Mon, 17 Feb 2025 19:20:39 +0800 > > > Yuquan Wang <wangyuquan1236@phytium.com.cn> wrote: > > > > > > > Add serial number parameter in the cxl persistent examples. > > > > > > > > Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn> > > > Looks good. I've queued it up on my gitlab staging tree, but > > > Michael if you want to pick this one directly that's fine as well. > > > > See no reason to, I was not even CC'd. > > Hi, Michael > > I'm sorry, this is my fault. I used "get_maintainer.pl" to check this > patch's maintainers but it shows "No maintainers found, printing recent > contributors". > I usually stage up multiple series together and send on to Michael. So it was be being lazy for a minor change rather than anything much that you did wrong. If I get time I'll post a series with this a few other patches later today. Jonathan > Yuquan > > > > > > I should be pushing out my gitlab tree shortly (bit of networking > > > fun to deal with). > > > > > > > --- > > > > docs/system/devices/cxl.rst | 18 +++++++++--------- > > > > 1 file changed, 9 insertions(+), 9 deletions(-) > > > > > > > > diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst > > > > index 882b036f5e..e307caf3f8 100644 > > > > --- a/docs/system/devices/cxl.rst > > > > +++ b/docs/system/devices/cxl.rst > > > > @@ -308,7 +308,7 @@ A very simple setup with just one directly attached CXL Type 3 Persistent Memory > > > > -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \ > > > > -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ > > > > -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ > > > > - -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ > > > > + -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0,sn=0x1 \ > > > > -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G > > > > > > > > A very simple setup with just one directly attached CXL Type 3 Volatile Memory device:: > > > > @@ -349,13 +349,13 @@ the CXL Type3 device directly attached (no switches).:: > > > > -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ > > > > -device pxb-cxl,bus_nr=222,bus=pcie.0,id=cxl.2 \ > > > > -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ > > > > - -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ > > > > + -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0,sn=0x1 \ > > > > -device cxl-rp,port=1,bus=cxl.1,id=root_port14,chassis=0,slot=3 \ > > > > - -device cxl-type3,bus=root_port14,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1 \ > > > > + -device cxl-type3,bus=root_port14,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1,sn=0x2 \ > > > > -device cxl-rp,port=0,bus=cxl.2,id=root_port15,chassis=0,slot=5 \ > > > > - -device cxl-type3,bus=root_port15,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2 \ > > > > + -device cxl-type3,bus=root_port15,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2,sn=0x3 \ > > > > -device cxl-rp,port=1,bus=cxl.2,id=root_port16,chassis=0,slot=6 \ > > > > - -device cxl-type3,bus=root_port16,persistent-memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3 \ > > > > + -device cxl-type3,bus=root_port16,persistent-memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3,sn=0x4 \ > > > > -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.targets.1=cxl.2,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k > > > > > > > > An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: > > > > @@ -375,13 +375,13 @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: > > > > -device cxl-rp,port=1,bus=cxl.1,id=root_port1,chassis=0,slot=1 \ > > > > -device cxl-upstream,bus=root_port0,id=us0 \ > > > > -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 \ > > > > - -device cxl-type3,bus=swport0,persistent-memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0 \ > > > > + -device cxl-type3,bus=swport0,persistent-memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0,sn=0x1 \ > > > > -device cxl-downstream,port=1,bus=us0,id=swport1,chassis=0,slot=5 \ > > > > - -device cxl-type3,bus=swport1,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1 \ > > > > + -device cxl-type3,bus=swport1,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1,sn=0x2 \ > > > > -device cxl-downstream,port=2,bus=us0,id=swport2,chassis=0,slot=6 \ > > > > - -device cxl-type3,bus=swport2,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2 \ > > > > + -device cxl-type3,bus=swport2,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2,sn=0x3 \ > > > > -device cxl-downstream,port=3,bus=us0,id=swport3,chassis=0,slot=7 \ > > > > - -device cxl-type3,bus=swport3,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3 \ > > > > + -device cxl-type3,bus=swport3,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3,sn=0x4 \ > > > > -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k > > > > > > > > Deprecations > > > 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 > Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.
> > On Tue, 4 Mar 2025 14:22:48 +0800 > Yuquan Wang <wangyuquan1236@phytium.com.cn> wrote: > > > > > > > On Thu, Feb 20, 2025 at 04:12:13PM +0000, Jonathan Cameron wrote: > > > > On Mon, 17 Feb 2025 19:20:39 +0800 > > > > Yuquan Wang <wangyuquan1236@phytium.com.cn> wrote: > > > > > > > > > Add serial number parameter in the cxl persistent examples. > > > > > > > > > > Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn> > > > > Looks good. I've queued it up on my gitlab staging tree, but > > > > Michael if you want to pick this one directly that's fine as well. > > > > > > See no reason to, I was not even CC'd. > > > > Hi, Michael > > > > I'm sorry, this is my fault. I used "get_maintainer.pl" to check this > > patch's maintainers but it shows "No maintainers found, printing recent > > contributors". > > > I usually stage up multiple series together and send on to Michael. > So it was be being lazy for a minor change rather than anything much > that you did wrong. > > If I get time I'll post a series with this a few other patches > later today. > > Jonathan > Thank you! BTW, I found a corner case in CXL numa node creation. Condition: 1) A UMA/NUMA system without SRAT, but with CEDT.CFMWS 2）Enable CONFIG_ACPI_NUMA Results: 1) acpi_numa_init: the fake_pxm will be 0 and send to acpi_parse_cfmws() 2）If dynamically create cxl ram region, the cxl memory would be assigned to node0 rather than a new node Confusions: 1) Is a numa system a requirement for CXL memory usage? 2) Should we forbid this situation by adding fake_pxm check and returning error in acpi_numa_init()? 3）Or we can add some kernel code to allow create these fake nodes on a system without SRAT? Yuquan 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.
On Wed, 5 Mar 2025 18:35:40 +0800 Yuquan Wang <wangyuquan1236@phytium.com.cn> wrote: > > > > On Tue, 4 Mar 2025 14:22:48 +0800 > > Yuquan Wang <wangyuquan1236@phytium.com.cn> wrote: > > > > > > > > > > On Thu, Feb 20, 2025 at 04:12:13PM +0000, Jonathan Cameron wrote: > > > > > On Mon, 17 Feb 2025 19:20:39 +0800 > > > > > Yuquan Wang <wangyuquan1236@phytium.com.cn> wrote: > > > > > > > > > > > Add serial number parameter in the cxl persistent examples. > > > > > > > > > > > > Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn> > > > > > Looks good. I've queued it up on my gitlab staging tree, but > > > > > Michael if you want to pick this one directly that's fine as well. > > > > > > > > See no reason to, I was not even CC'd. > > > > > > Hi, Michael > > > > > > I'm sorry, this is my fault. I used "get_maintainer.pl" to check this > > > patch's maintainers but it shows "No maintainers found, printing recent > > > contributors". > > > > > I usually stage up multiple series together and send on to Michael. > > So it was be being lazy for a minor change rather than anything much > > that you did wrong. > > > > If I get time I'll post a series with this a few other patches > > later today. > > > > Jonathan > > > Thank you! > > BTW, I found a corner case in CXL numa node creation. > > Condition: > 1) A UMA/NUMA system without SRAT, but with CEDT.CFMWS > 2）Enable CONFIG_ACPI_NUMA > > Results: > 1) acpi_numa_init: the fake_pxm will be 0 and send to acpi_parse_cfmws() > 2）If dynamically create cxl ram region, the cxl memory would be assigned > to node0 rather than a new node > > Confusions: > 1) Is a numa system a requirement for CXL memory usage? Obviously discussion has gone on elsewhere, but I'd say in general it would be a bad idea to not have an SRAT because the moment we add CXL it is definitely a NUMA system and we want the Generic Port entry to allow us to get perf information. So I wouldn't mind if we fail CXL init in this case, but maybe it is worth papering over things. Jonathan > 2) Should we forbid this situation by adding fake_pxm check and returning > error in acpi_numa_init()? > 3）Or we can add some kernel code to allow create these fake nodes on a > system without SRAT? > > Yuquan > > > > > > 信息安全声明：本邮件包含信息归发件人所在组织所有,发件人所在组织对该邮件拥有所有权利。请接收者注意保密,未经发件人书面许可,不得向任何第三方组织和个人透露本邮件所含信息。 > Information Security Notice: The information contained in this mail is solely property of the sender's organization.This mail communication is confidential.Recipients named above are obligated to maintain secrecy and are not permitted to disclose the contents of this communication to others.
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index 882b036f5e..e307caf3f8 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -308,7 +308,7 @@ A very simple setup with just one directly attached CXL Type 3 Persistent Memory -object memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M \ -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ - -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ + -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0,sn=0x1 \ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G A very simple setup with just one directly attached CXL Type 3 Volatile Memory device:: @@ -349,13 +349,13 @@ the CXL Type3 device directly attached (no switches).:: -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ -device pxb-cxl,bus_nr=222,bus=pcie.0,id=cxl.2 \ -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \ - -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \ + -device cxl-type3,bus=root_port13,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0,sn=0x1 \ -device cxl-rp,port=1,bus=cxl.1,id=root_port14,chassis=0,slot=3 \ - -device cxl-type3,bus=root_port14,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1 \ + -device cxl-type3,bus=root_port14,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1,sn=0x2 \ -device cxl-rp,port=0,bus=cxl.2,id=root_port15,chassis=0,slot=5 \ - -device cxl-type3,bus=root_port15,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2 \ + -device cxl-type3,bus=root_port15,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2,sn=0x3 \ -device cxl-rp,port=1,bus=cxl.2,id=root_port16,chassis=0,slot=6 \ - -device cxl-type3,bus=root_port16,persistent-memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3 \ + -device cxl-type3,bus=root_port16,persistent-memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3,sn=0x4 \ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.targets.1=cxl.2,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: @@ -375,13 +375,13 @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: -device cxl-rp,port=1,bus=cxl.1,id=root_port1,chassis=0,slot=1 \ -device cxl-upstream,bus=root_port0,id=us0 \ -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 \ - -device cxl-type3,bus=swport0,persistent-memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0 \ + -device cxl-type3,bus=swport0,persistent-memdev=cxl-mem0,lsa=cxl-lsa0,id=cxl-pmem0,sn=0x1 \ -device cxl-downstream,port=1,bus=us0,id=swport1,chassis=0,slot=5 \ - -device cxl-type3,bus=swport1,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1 \ + -device cxl-type3,bus=swport1,persistent-memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem1,sn=0x2 \ -device cxl-downstream,port=2,bus=us0,id=swport2,chassis=0,slot=6 \ - -device cxl-type3,bus=swport2,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2 \ + -device cxl-type3,bus=swport2,persistent-memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem2,sn=0x3 \ -device cxl-downstream,port=3,bus=us0,id=swport3,chassis=0,slot=7 \ - -device cxl-type3,bus=swport3,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3 \ + -device cxl-type3,bus=swport3,persistent-memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem3,sn=0x4 \ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k Deprecations
Add serial number parameter in the cxl persistent examples. Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn> --- docs/system/devices/cxl.rst | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)