diff mbox series

[3/7] target/riscv: assert argument to set_satp_mode_max_supported is valid

Message ID 20250218165757.554178-4-pbonzini@redhat.com (mailing list archive)
State New
Headers show
Series target/riscv: store max SATP mode as a single integer in RISCVCPUConfig | expand

Commit Message

Paolo Bonzini Feb. 18, 2025, 4:57 p.m. UTC
Check that the argument to set_satp_mode_max_supported is valid for
the MXL value of the CPU.  It would be a bug in the CPU definition
if it weren't.

In fact, there is such a bug in riscv_bare_cpu_init(): not just
SV32 is not a valid VM mode for 64-bit CPUs, SV64 is not a
valid VM mode at all, not yet at least.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/riscv/cpu.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

Comments

Alistair Francis March 6, 2025, 1:23 a.m. UTC | #1
On Wed, Feb 19, 2025 at 2:58 AM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> Check that the argument to set_satp_mode_max_supported is valid for
> the MXL value of the CPU.  It would be a bug in the CPU definition
> if it weren't.
>
> In fact, there is such a bug in riscv_bare_cpu_init(): not just
> SV32 is not a valid VM mode for 64-bit CPUs, SV64 is not a
> valid VM mode at all, not yet at least.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index cca24b9f1fc..7950b6447f8 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -442,6 +442,8 @@ static void set_satp_mode_max_supported(RISCVCPU *cpu,
>              cpu->cfg.satp_mode.supported |= (1 << i);
>          }
>      }
> +
> +    assert(cpu->cfg.satp_mode.supported & (1 << satp_mode));
>  }
>
>  /* Set the satp mode to the max supported */
> @@ -1502,7 +1504,9 @@ static void riscv_bare_cpu_init(Object *obj)
>       * satp_mode manually (see set_satp_mode_default()).
>       */
>  #ifndef CONFIG_USER_ONLY
> -    set_satp_mode_max_supported(cpu, VM_1_10_SV64);
> +    set_satp_mode_max_supported(RISCV_CPU(obj),
> +        riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
> +        VM_1_10_SV32 : VM_1_10_SV57);
>  #endif
>  }
>
> --
> 2.48.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cca24b9f1fc..7950b6447f8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -442,6 +442,8 @@  static void set_satp_mode_max_supported(RISCVCPU *cpu,
             cpu->cfg.satp_mode.supported |= (1 << i);
         }
     }
+
+    assert(cpu->cfg.satp_mode.supported & (1 << satp_mode));
 }
 
 /* Set the satp mode to the max supported */
@@ -1502,7 +1504,9 @@  static void riscv_bare_cpu_init(Object *obj)
      * satp_mode manually (see set_satp_mode_default()).
      */
 #ifndef CONFIG_USER_ONLY
-    set_satp_mode_max_supported(cpu, VM_1_10_SV64);
+    set_satp_mode_max_supported(RISCV_CPU(obj),
+        riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
+        VM_1_10_SV32 : VM_1_10_SV57);
 #endif
 }