| Message ID | 20250218165757.554178-8-pbonzini@redhat.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: store max SATP mode as a single integer in RISCVCPUConfig | expand |
On Wed, Feb 19, 2025 at 3:00 AM Paolo Bonzini <pbonzini@redhat.com> wrote: > > They are used to provide the nice QOM properties for svNN, > but the canonical source of the CPU configuration is now > cpu->cfg.max_satp_mode. Store them in the ArchCPU struct. > > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.h | 14 ++++++++++++++ > target/riscv/cpu_cfg.h | 14 -------------- > target/riscv/cpu.c | 32 ++++++++++++++++---------------- > 3 files changed, 30 insertions(+), 30 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index f9b223bf8a7..df7a05e7d15 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -492,6 +492,19 @@ struct CPUArchState { > uint64_t rnmi_excpvec; > }; > > +/* > + * map is a 16-bit bitmap: the most significant set bit in map is the maximum > + * satp mode that is supported. It may be chosen by the user and must respect > + * what qemu implements (valid_1_10_32/64) and what the hw is capable of > + * (supported bitmap below). > + * > + * init is a 16-bit bitmap used to make sure the user selected a correct > + * configuration as per the specification. > + */ > +typedef struct { > + uint16_t map, init; > +} RISCVSATPModes; > + > /* > * RISCVCPU: > * @env: #CPURISCVState > @@ -508,6 +521,7 @@ struct ArchCPU { > > /* Configuration Settings */ > RISCVCPUConfig cfg; > + RISCVSATPModes satp_modes; > > QEMUTimer *pmu_timer; > /* A bitmask of Available programmable counters */ > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 1d7fff8decd..7b7067d5bee 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -21,19 +21,6 @@ > #ifndef RISCV_CPU_CFG_H > #define RISCV_CPU_CFG_H > > -/* > - * map is a 16-bit bitmap: the most significant set bit in map is the maximum > - * satp mode that is supported. It may be chosen by the user and must respect > - * what qemu implements (valid_1_10_32/64) and what the hw is capable of > - * (supported bitmap below). > - * > - * init is a 16-bit bitmap used to make sure the user selected a correct > - * configuration as per the specification. > - */ > -typedef struct { > - uint16_t map, init; > -} RISCVSATPMap; > - > struct RISCVCPUConfig { > bool ext_zba; > bool ext_zbb; > @@ -191,7 +178,6 @@ struct RISCVCPUConfig { > > #ifndef CONFIG_USER_ONLY > int8_t max_satp_mode; > - RISCVSATPMap satp_mode; > #endif > }; > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 86a048b62c5..8ab7fe2e286 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1197,8 +1197,8 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > return; > } > > - if (cpu->cfg.satp_mode.map == 0) { > - if (cpu->cfg.satp_mode.init == 0) { > + if (cpu->satp_modes.map == 0) { > + if (cpu->satp_modes.init == 0) { > /* If unset by the user, we fallback to the default satp mode. */ > set_satp_mode_default_map(cpu); > } else { > @@ -1208,7 +1208,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > * valid_vm_1_10_32/64. > */ > for (int i = 1; i < 16; ++i) { > - if ((cpu->cfg.satp_mode.init & (1 << i)) && > + if ((cpu->satp_modes.init & (1 << i)) && > supported & (1 << i)) { > for (int j = i - 1; j >= 0; --j) { > if (supported & (1 << j)) { > @@ -1222,7 +1222,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > return; > } > > - satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > + satp_mode_map_max = satp_mode_max_from_map(cpu->satp_modes.map); > > /* Make sure the user asked for a supported configuration (HW and qemu) */ > if (satp_mode_map_max > cpu->cfg.max_satp_mode) { > @@ -1238,8 +1238,8 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > */ > if (!rv32) { > for (int i = satp_mode_map_max - 1; i >= 0; --i) { > - if (!(cpu->cfg.satp_mode.map & (1 << i)) && > - (cpu->cfg.satp_mode.init & (1 << i)) && > + if (!(cpu->satp_modes.map & (1 << i)) && > + (cpu->satp_modes.init & (1 << i)) && > (supported & (1 << i))) { > error_setg(errp, "cannot disable %s satp mode if %s " > "is enabled", satp_mode_str(i, false), > @@ -1327,11 +1327,11 @@ bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu) > static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > void *opaque, Error **errp) > { > - RISCVSATPMap *satp_map = opaque; > + RISCVSATPModes *satp_modes = opaque; > uint8_t satp = satp_mode_from_str(name); > bool value; > > - value = satp_map->map & (1 << satp); > + value = satp_modes->map & (1 << satp); > > visit_type_bool(v, name, &value, errp); > } > @@ -1339,7 +1339,7 @@ static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > void *opaque, Error **errp) > { > - RISCVSATPMap *satp_map = opaque; > + RISCVSATPModes *satp_modes = opaque; > uint8_t satp = satp_mode_from_str(name); > bool value; > > @@ -1347,8 +1347,8 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > return; > } > > - satp_map->map = deposit32(satp_map->map, satp, 1, value); > - satp_map->init |= 1 << satp; > + satp_modes->map = deposit32(satp_modes->map, satp, 1, value); > + satp_modes->init |= 1 << satp; > } > > void riscv_add_satp_mode_properties(Object *obj) > @@ -1357,16 +1357,16 @@ void riscv_add_satp_mode_properties(Object *obj) > > if (cpu->env.misa_mxl == MXL_RV32) { > object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + cpu_riscv_set_satp, NULL, &cpu->satp_modes); > } else { > object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + cpu_riscv_set_satp, NULL, &cpu->satp_modes); > object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + cpu_riscv_set_satp, NULL, &cpu->satp_modes); > object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + cpu_riscv_set_satp, NULL, &cpu->satp_modes); > object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + cpu_riscv_set_satp, NULL, &cpu->satp_modes); > } > } > > -- > 2.48.1 > >
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f9b223bf8a7..df7a05e7d15 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -492,6 +492,19 @@ struct CPUArchState { uint64_t rnmi_excpvec; }; +/* + * map is a 16-bit bitmap: the most significant set bit in map is the maximum + * satp mode that is supported. It may be chosen by the user and must respect + * what qemu implements (valid_1_10_32/64) and what the hw is capable of + * (supported bitmap below). + * + * init is a 16-bit bitmap used to make sure the user selected a correct + * configuration as per the specification. + */ +typedef struct { + uint16_t map, init; +} RISCVSATPModes; + /* * RISCVCPU: * @env: #CPURISCVState @@ -508,6 +521,7 @@ struct ArchCPU { /* Configuration Settings */ RISCVCPUConfig cfg; + RISCVSATPModes satp_modes; QEMUTimer *pmu_timer; /* A bitmask of Available programmable counters */ diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 1d7fff8decd..7b7067d5bee 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -21,19 +21,6 @@ #ifndef RISCV_CPU_CFG_H #define RISCV_CPU_CFG_H -/* - * map is a 16-bit bitmap: the most significant set bit in map is the maximum - * satp mode that is supported. It may be chosen by the user and must respect - * what qemu implements (valid_1_10_32/64) and what the hw is capable of - * (supported bitmap below). - * - * init is a 16-bit bitmap used to make sure the user selected a correct - * configuration as per the specification. - */ -typedef struct { - uint16_t map, init; -} RISCVSATPMap; - struct RISCVCPUConfig { bool ext_zba; bool ext_zbb; @@ -191,7 +178,6 @@ struct RISCVCPUConfig { #ifndef CONFIG_USER_ONLY int8_t max_satp_mode; - RISCVSATPMap satp_mode; #endif }; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 86a048b62c5..8ab7fe2e286 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1197,8 +1197,8 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) return; } - if (cpu->cfg.satp_mode.map == 0) { - if (cpu->cfg.satp_mode.init == 0) { + if (cpu->satp_modes.map == 0) { + if (cpu->satp_modes.init == 0) { /* If unset by the user, we fallback to the default satp mode. */ set_satp_mode_default_map(cpu); } else { @@ -1208,7 +1208,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) * valid_vm_1_10_32/64. */ for (int i = 1; i < 16; ++i) { - if ((cpu->cfg.satp_mode.init & (1 << i)) && + if ((cpu->satp_modes.init & (1 << i)) && supported & (1 << i)) { for (int j = i - 1; j >= 0; --j) { if (supported & (1 << j)) { @@ -1222,7 +1222,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) return; } - satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + satp_mode_map_max = satp_mode_max_from_map(cpu->satp_modes.map); /* Make sure the user asked for a supported configuration (HW and qemu) */ if (satp_mode_map_max > cpu->cfg.max_satp_mode) { @@ -1238,8 +1238,8 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) */ if (!rv32) { for (int i = satp_mode_map_max - 1; i >= 0; --i) { - if (!(cpu->cfg.satp_mode.map & (1 << i)) && - (cpu->cfg.satp_mode.init & (1 << i)) && + if (!(cpu->satp_modes.map & (1 << i)) && + (cpu->satp_modes.init & (1 << i)) && (supported & (1 << i))) { error_setg(errp, "cannot disable %s satp mode if %s " "is enabled", satp_mode_str(i, false), @@ -1327,11 +1327,11 @@ bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu) static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - RISCVSATPMap *satp_map = opaque; + RISCVSATPModes *satp_modes = opaque; uint8_t satp = satp_mode_from_str(name); bool value; - value = satp_map->map & (1 << satp); + value = satp_modes->map & (1 << satp); visit_type_bool(v, name, &value, errp); } @@ -1339,7 +1339,7 @@ static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - RISCVSATPMap *satp_map = opaque; + RISCVSATPModes *satp_modes = opaque; uint8_t satp = satp_mode_from_str(name); bool value; @@ -1347,8 +1347,8 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, return; } - satp_map->map = deposit32(satp_map->map, satp, 1, value); - satp_map->init |= 1 << satp; + satp_modes->map = deposit32(satp_modes->map, satp, 1, value); + satp_modes->init |= 1 << satp; } void riscv_add_satp_mode_properties(Object *obj) @@ -1357,16 +1357,16 @@ void riscv_add_satp_mode_properties(Object *obj) if (cpu->env.misa_mxl == MXL_RV32) { object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + cpu_riscv_set_satp, NULL, &cpu->satp_modes); } else { object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + cpu_riscv_set_satp, NULL, &cpu->satp_modes); object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + cpu_riscv_set_satp, NULL, &cpu->satp_modes); object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + cpu_riscv_set_satp, NULL, &cpu->satp_modes); object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + cpu_riscv_set_satp, NULL, &cpu->satp_modes); } }
They are used to provide the nice QOM properties for svNN, but the canonical source of the CPU configuration is now cpu->cfg.max_satp_mode. Store them in the ArchCPU struct. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- target/riscv/cpu.h | 14 ++++++++++++++ target/riscv/cpu_cfg.h | 14 -------------- target/riscv/cpu.c | 32 ++++++++++++++++---------------- 3 files changed, 30 insertions(+), 30 deletions(-)