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[77.11.167.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abba4b9ee98sm1240515466b.167.2025.02.23.03.47.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Feb 2025 03:47:34 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Laurent Vivier , Andrey Smirnov , Bernhard Beschow , Fabiano Rosas , Alistair Francis , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-?= =?utf-8?q?Daud=C3=A9?= Subject: [PATCH v2 10/18] hw/arm/fsl-imx8mp: Add I2C controllers Date: Sun, 23 Feb 2025 12:47:00 +0100 Message-ID: <20250223114708.1780-11-shentey@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250223114708.1780-1-shentey@gmail.com> References: <20250223114708.1780-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=shentey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow --- docs/system/arm/imx8mp-evk.rst | 1 + include/hw/arm/fsl-imx8mp.h | 11 +++++++++++ hw/arm/fsl-imx8mp.c | 29 +++++++++++++++++++++++++++++ hw/arm/Kconfig | 2 ++ 4 files changed, 43 insertions(+) diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst index 37d3630d09..ef0d997250 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8mp-evk.rst @@ -15,6 +15,7 @@ The ``imx8mp-evk`` machine implements the following devices: * 3 USDHC Storage Controllers * 1 Designware PCI Express Controller * 5 GPIO Controllers + * 6 I2C Controllers * Secure Non-Volatile Storage (SNVS) including an RTC * Clock Tree diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h index 18ea52d083..2590056627 100644 --- a/include/hw/arm/fsl-imx8mp.h +++ b/include/hw/arm/fsl-imx8mp.h @@ -12,6 +12,7 @@ #include "cpu.h" #include "hw/char/imx_serial.h" #include "hw/gpio/imx_gpio.h" +#include "hw/i2c/imx_i2c.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" @@ -31,6 +32,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mpState, FSL_IMX8MP) enum FslImx8mpConfiguration { FSL_IMX8MP_NUM_CPUS = 4, FSL_IMX8MP_NUM_GPIOS = 5, + FSL_IMX8MP_NUM_I2CS = 6, FSL_IMX8MP_NUM_IRQS = 160, FSL_IMX8MP_NUM_UARTS = 4, FSL_IMX8MP_NUM_USDHCS = 3, @@ -45,6 +47,7 @@ struct FslImx8mpState { IMX8MPCCMState ccm; IMX8MPAnalogState analog; IMX7SNVSState snvs; + IMXI2CState i2c[FSL_IMX8MP_NUM_I2CS]; IMXSerialState uart[FSL_IMX8MP_NUM_UARTS]; SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS]; DesignwarePCIEHost pcie; @@ -205,6 +208,11 @@ enum FslImx8mpIrqs { FSL_IMX8MP_UART5_IRQ = 30, FSL_IMX8MP_UART6_IRQ = 16, + FSL_IMX8MP_I2C1_IRQ = 35, + FSL_IMX8MP_I2C2_IRQ = 36, + FSL_IMX8MP_I2C3_IRQ = 37, + FSL_IMX8MP_I2C4_IRQ = 38, + FSL_IMX8MP_GPIO1_LOW_IRQ = 64, FSL_IMX8MP_GPIO1_HIGH_IRQ = 65, FSL_IMX8MP_GPIO2_LOW_IRQ = 66, @@ -216,6 +224,9 @@ enum FslImx8mpIrqs { FSL_IMX8MP_GPIO5_LOW_IRQ = 72, FSL_IMX8MP_GPIO5_HIGH_IRQ = 73, + FSL_IMX8MP_I2C5_IRQ = 76, + FSL_IMX8MP_I2C6_IRQ = 77, + FSL_IMX8MP_PCI_INTA_IRQ = 126, FSL_IMX8MP_PCI_INTB_IRQ = 125, FSL_IMX8MP_PCI_INTC_IRQ = 124, diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 456fa47dc7..3da81e28ca 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -208,6 +208,11 @@ static void fsl_imx8mp_init(Object *obj) object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); } + for (i = 0; i < FSL_IMX8MP_NUM_I2CS; i++) { + g_autofree char *name = g_strdup_printf("i2c%d", i + 1); + object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); + } + for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) { g_autofree char *name = g_strdup_printf("gpio%d", i + 1); object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); @@ -360,6 +365,29 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(gicdev, serial_table[i].irq)); } + /* I2Cs */ + for (i = 0; i < FSL_IMX8MP_NUM_I2CS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } i2c_table[FSL_IMX8MP_NUM_I2CS] = { + { fsl_imx8mp_memmap[FSL_IMX8MP_I2C1].addr, FSL_IMX8MP_I2C1_IRQ }, + { fsl_imx8mp_memmap[FSL_IMX8MP_I2C2].addr, FSL_IMX8MP_I2C2_IRQ }, + { fsl_imx8mp_memmap[FSL_IMX8MP_I2C3].addr, FSL_IMX8MP_I2C3_IRQ }, + { fsl_imx8mp_memmap[FSL_IMX8MP_I2C4].addr, FSL_IMX8MP_I2C4_IRQ }, + { fsl_imx8mp_memmap[FSL_IMX8MP_I2C5].addr, FSL_IMX8MP_I2C5_IRQ }, + { fsl_imx8mp_memmap[FSL_IMX8MP_I2C6].addr, FSL_IMX8MP_I2C6_IRQ }, + }; + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, + qdev_get_gpio_in(gicdev, i2c_table[i].irq)); + } + /* GPIOs */ for (i = 0; i < FSL_IMX8MP_NUM_GPIOS; i++) { static const struct { @@ -470,6 +498,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error **errp) case FSL_IMX8MP_GIC_DIST: case FSL_IMX8MP_GIC_REDIST: case FSL_IMX8MP_GPIO1 ... FSL_IMX8MP_GPIO5: + case FSL_IMX8MP_I2C1 ... FSL_IMX8MP_I2C6: case FSL_IMX8MP_PCIE1: case FSL_IMX8MP_PCIE_PHY1: case FSL_IMX8MP_RAM: diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index be5a2c02b7..28ae409c85 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -595,11 +595,13 @@ config FSL_IMX7 config FSL_IMX8MP bool + imply I2C_DEVICES imply PCI_DEVICES select ARM_GIC select FSL_IMX8MP_ANALOG select FSL_IMX8MP_CCM select IMX + select IMX_I2C select PCI_EXPRESS_DESIGNWARE select PCI_EXPRESS_FSL_IMX8M_PHY select SDHCI