| Message ID | 20250225075622.305515-5-jamin_lin@aspeedtech.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Support HACE to AST2700 (resend) | expand |
On 2/25/25 08:56, Jamin Lin wrote: > Currently, it does not support the CRYPT command. Instead, it only sends an > interrupt to notify the firmware that the crypt command has completed. > It is a temporary workaround to resolve the boot issue in the Crypto Manager > Self Test. > > Introduce a new "use_crypt_workaround" class attribute and set it to true in > the AST2700 HACE model to enable this workaround by default for AST2700. > > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Thanks, C. > --- > include/hw/misc/aspeed_hace.h | 1 + > hw/misc/aspeed_hace.c | 23 +++++++++++++++++++++++ > 2 files changed, 24 insertions(+) > > diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h > index d13fd3da07..5d4aa19cfe 100644 > --- a/include/hw/misc/aspeed_hace.h > +++ b/include/hw/misc/aspeed_hace.h > @@ -50,6 +50,7 @@ struct AspeedHACEClass { > uint32_t dest_mask; > uint32_t key_mask; > uint32_t hash_mask; > + bool raise_crypt_interrupt_workaround; > }; > > #endif /* ASPEED_HACE_H */ > diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c > index 86422cb3be..32a5dbded3 100644 > --- a/hw/misc/aspeed_hace.c > +++ b/hw/misc/aspeed_hace.c > @@ -59,6 +59,7 @@ > /* Other cmd bits */ > #define HASH_IRQ_EN BIT(9) > #define HASH_SG_EN BIT(18) > +#define CRYPT_IRQ_EN BIT(12) > /* Scatter-gather data list */ > #define SG_LIST_LEN_SIZE 4 > #define SG_LIST_LEN_MASK 0x0FFFFFFF > @@ -343,6 +344,15 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, > qemu_irq_lower(s->irq); > } > } > + if (ahc->raise_crypt_interrupt_workaround) { > + if (data & CRYPT_IRQ) { > + data &= ~CRYPT_IRQ; > + > + if (s->regs[addr] & CRYPT_IRQ) { > + qemu_irq_lower(s->irq); > + } > + } > + } > break; > case R_HASH_SRC: > data &= ahc->src_mask; > @@ -388,6 +398,12 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, > case R_CRYPT_CMD: > qemu_log_mask(LOG_UNIMP, "%s: Crypt commands not implemented\n", > __func__); > + if (ahc->raise_crypt_interrupt_workaround) { > + s->regs[R_STATUS] |= CRYPT_IRQ; > + if (data & CRYPT_IRQ_EN) { > + qemu_irq_raise(s->irq); > + } > + } > break; > default: > break; > @@ -563,6 +579,13 @@ static void aspeed_ast2700_hace_class_init(ObjectClass *klass, void *data) > ahc->dest_mask = 0x7FFFFFF8; > ahc->key_mask = 0x7FFFFFF8; > ahc->hash_mask = 0x00147FFF; > + > + /* > + * Currently, it does not support the CRYPT command. Instead, it only > + * sends an interrupt to notify the firmware that the crypt command > + * has completed. It is a temporary workaround. > + */ > + ahc->raise_crypt_interrupt_workaround = true; > } > > static const TypeInfo aspeed_ast2700_hace_info = {
diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h index d13fd3da07..5d4aa19cfe 100644 --- a/include/hw/misc/aspeed_hace.h +++ b/include/hw/misc/aspeed_hace.h @@ -50,6 +50,7 @@ struct AspeedHACEClass { uint32_t dest_mask; uint32_t key_mask; uint32_t hash_mask; + bool raise_crypt_interrupt_workaround; }; #endif /* ASPEED_HACE_H */ diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 86422cb3be..32a5dbded3 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -59,6 +59,7 @@ /* Other cmd bits */ #define HASH_IRQ_EN BIT(9) #define HASH_SG_EN BIT(18) +#define CRYPT_IRQ_EN BIT(12) /* Scatter-gather data list */ #define SG_LIST_LEN_SIZE 4 #define SG_LIST_LEN_MASK 0x0FFFFFFF @@ -343,6 +344,15 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, qemu_irq_lower(s->irq); } } + if (ahc->raise_crypt_interrupt_workaround) { + if (data & CRYPT_IRQ) { + data &= ~CRYPT_IRQ; + + if (s->regs[addr] & CRYPT_IRQ) { + qemu_irq_lower(s->irq); + } + } + } break; case R_HASH_SRC: data &= ahc->src_mask; @@ -388,6 +398,12 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, case R_CRYPT_CMD: qemu_log_mask(LOG_UNIMP, "%s: Crypt commands not implemented\n", __func__); + if (ahc->raise_crypt_interrupt_workaround) { + s->regs[R_STATUS] |= CRYPT_IRQ; + if (data & CRYPT_IRQ_EN) { + qemu_irq_raise(s->irq); + } + } break; default: break; @@ -563,6 +579,13 @@ static void aspeed_ast2700_hace_class_init(ObjectClass *klass, void *data) ahc->dest_mask = 0x7FFFFFF8; ahc->key_mask = 0x7FFFFFF8; ahc->hash_mask = 0x00147FFF; + + /* + * Currently, it does not support the CRYPT command. Instead, it only + * sends an interrupt to notify the firmware that the crypt command + * has completed. It is a temporary workaround. + */ + ahc->raise_crypt_interrupt_workaround = true; } static const TypeInfo aspeed_ast2700_hace_info = {
Currently, it does not support the CRYPT command. Instead, it only sends an interrupt to notify the firmware that the crypt command has completed. It is a temporary workaround to resolve the boot issue in the Crypto Manager Self Test. Introduce a new "use_crypt_workaround" class attribute and set it to true in the AST2700 HACE model to enable this workaround by default for AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- include/hw/misc/aspeed_hace.h | 1 + hw/misc/aspeed_hace.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+)