| Message ID | 20250301052628.1011210-14-brian.cain@oss.qualcomm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hexagon system emu, part 1/3 | expand |
> -----Original Message----- > From: Brian Cain <brian.cain@oss.qualcomm.com> > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org; > philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng; > quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com; > alex.bennee@linaro.org; quic_mburton@quicinc.com; > sidneym@quicinc.com; Brian Cain <bcain@quicinc.com> > Subject: [PATCH 13/38] target/hexagon: Define DCache states > > From: Brian Cain <bcain@quicinc.com> > > Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com> > --- > target/hexagon/cpu_bits.h | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index > 6582bb4f16..5d26815eb9 100644 > --- a/target/hexagon/cpu_bits.h > +++ b/target/hexagon/cpu_bits.h > @@ -41,6 +41,13 @@ enum hex_cause { > HEX_CAUSE_PRIV_USER_NO_SINSN = 0x01b, }; > > +enum data_cache_state { > + HEX_DC_STATE_INVALID = 0x0, > + HEX_DC_STATE_VALID = 0x1, > + HEX_DC_STATE_RESERVED = 0x2, > + HEX_DC_STATE_UNUSED_WT = 0x3, > +}; > + Why is this needed? QEMU doesn't model the data cache.
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index 6582bb4f16..5d26815eb9 100644 --- a/target/hexagon/cpu_bits.h +++ b/target/hexagon/cpu_bits.h @@ -41,6 +41,13 @@ enum hex_cause { HEX_CAUSE_PRIV_USER_NO_SINSN = 0x01b, }; +enum data_cache_state { + HEX_DC_STATE_INVALID = 0x0, + HEX_DC_STATE_VALID = 0x1, + HEX_DC_STATE_RESERVED = 0x2, + HEX_DC_STATE_UNUSED_WT = 0x3, +}; + #define PACKET_WORDS_MAX 4 static inline uint32_t parse_bits(uint32_t encoding)