| Message ID | 20250301173751.9446-1-jason.chien@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] hw/riscv/riscv-iommu: Fix process directory table walk | expand |
On 3/1/25 2:37 PM, Jason Chien wrote: > The PPN field in a non-leaf PDT entry is positioned differently from that > in a leaf PDT entry. The original implementation incorrectly used the leaf > entry's PPN mask to extract the PPN from a non-leaf entry, leading to an > erroneous page table walk. > > This commit introduces new macros to properly define the fields for > non-leaf PDT entries and corrects the page table walk. > > Signed-off-by: Jason Chien <jason.chien@sifive.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > hw/riscv/riscv-iommu-bits.h | 6 +++++- > hw/riscv/riscv-iommu.c | 4 ++-- > 2 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h > index b7cb1bc736..1017d73fc6 100644 > --- a/hw/riscv/riscv-iommu-bits.h > +++ b/hw/riscv/riscv-iommu-bits.h > @@ -415,12 +415,16 @@ enum riscv_iommu_fq_causes { > #define RISCV_IOMMU_DC_MSIPTP_MODE_OFF 0 > #define RISCV_IOMMU_DC_MSIPTP_MODE_FLAT 1 > > +/* 2.2 Process Directory Table */ > +#define RISCV_IOMMU_PDTE_VALID BIT_ULL(0) > +#define RISCV_IOMMU_PDTE_PPN RISCV_IOMMU_PPN_FIELD > + > /* Translation attributes fields */ > #define RISCV_IOMMU_PC_TA_V BIT_ULL(0) > #define RISCV_IOMMU_PC_TA_RESERVED GENMASK_ULL(63, 32) > > /* First stage context fields */ > -#define RISCV_IOMMU_PC_FSC_PPN GENMASK_ULL(43, 0) > +#define RISCV_IOMMU_PC_FSC_PPN RISCV_IOMMU_ATP_PPN_FIELD > #define RISCV_IOMMU_PC_FSC_RESERVED GENMASK_ULL(59, 44) > > enum riscv_iommu_fq_ttypes { > diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c > index d46beb2d64..76e0fcd873 100644 > --- a/hw/riscv/riscv-iommu.c > +++ b/hw/riscv/riscv-iommu.c > @@ -1042,10 +1042,10 @@ static int riscv_iommu_ctx_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx) > return RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT; > } > le64_to_cpus(&de); > - if (!(de & RISCV_IOMMU_PC_TA_V)) { > + if (!(de & RISCV_IOMMU_PDTE_VALID)) { > return RISCV_IOMMU_FQ_CAUSE_PDT_INVALID; > } > - addr = PPN_PHYS(get_field(de, RISCV_IOMMU_PC_FSC_PPN)); > + addr = PPN_PHYS(get_field(de, RISCV_IOMMU_PDTE_PPN)); > } > > riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_PD_WALK);
On Sun, Mar 2, 2025 at 3:39 AM Jason Chien <jason.chien@sifive.com> wrote: > > The PPN field in a non-leaf PDT entry is positioned differently from that > in a leaf PDT entry. The original implementation incorrectly used the leaf > entry's PPN mask to extract the PPN from a non-leaf entry, leading to an > erroneous page table walk. > > This commit introduces new macros to properly define the fields for > non-leaf PDT entries and corrects the page table walk. > > Signed-off-by: Jason Chien <jason.chien@sifive.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > hw/riscv/riscv-iommu-bits.h | 6 +++++- > hw/riscv/riscv-iommu.c | 4 ++-- > 2 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h > index b7cb1bc736..1017d73fc6 100644 > --- a/hw/riscv/riscv-iommu-bits.h > +++ b/hw/riscv/riscv-iommu-bits.h > @@ -415,12 +415,16 @@ enum riscv_iommu_fq_causes { > #define RISCV_IOMMU_DC_MSIPTP_MODE_OFF 0 > #define RISCV_IOMMU_DC_MSIPTP_MODE_FLAT 1 > > +/* 2.2 Process Directory Table */ > +#define RISCV_IOMMU_PDTE_VALID BIT_ULL(0) > +#define RISCV_IOMMU_PDTE_PPN RISCV_IOMMU_PPN_FIELD > + > /* Translation attributes fields */ > #define RISCV_IOMMU_PC_TA_V BIT_ULL(0) > #define RISCV_IOMMU_PC_TA_RESERVED GENMASK_ULL(63, 32) > > /* First stage context fields */ > -#define RISCV_IOMMU_PC_FSC_PPN GENMASK_ULL(43, 0) > +#define RISCV_IOMMU_PC_FSC_PPN RISCV_IOMMU_ATP_PPN_FIELD > #define RISCV_IOMMU_PC_FSC_RESERVED GENMASK_ULL(59, 44) > > enum riscv_iommu_fq_ttypes { > diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c > index d46beb2d64..76e0fcd873 100644 > --- a/hw/riscv/riscv-iommu.c > +++ b/hw/riscv/riscv-iommu.c > @@ -1042,10 +1042,10 @@ static int riscv_iommu_ctx_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx) > return RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT; > } > le64_to_cpus(&de); > - if (!(de & RISCV_IOMMU_PC_TA_V)) { > + if (!(de & RISCV_IOMMU_PDTE_VALID)) { > return RISCV_IOMMU_FQ_CAUSE_PDT_INVALID; > } > - addr = PPN_PHYS(get_field(de, RISCV_IOMMU_PC_FSC_PPN)); > + addr = PPN_PHYS(get_field(de, RISCV_IOMMU_PDTE_PPN)); > } > > riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_PD_WALK); > -- > 2.43.2 > >
diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h index b7cb1bc736..1017d73fc6 100644 --- a/hw/riscv/riscv-iommu-bits.h +++ b/hw/riscv/riscv-iommu-bits.h @@ -415,12 +415,16 @@ enum riscv_iommu_fq_causes { #define RISCV_IOMMU_DC_MSIPTP_MODE_OFF 0 #define RISCV_IOMMU_DC_MSIPTP_MODE_FLAT 1 +/* 2.2 Process Directory Table */ +#define RISCV_IOMMU_PDTE_VALID BIT_ULL(0) +#define RISCV_IOMMU_PDTE_PPN RISCV_IOMMU_PPN_FIELD + /* Translation attributes fields */ #define RISCV_IOMMU_PC_TA_V BIT_ULL(0) #define RISCV_IOMMU_PC_TA_RESERVED GENMASK_ULL(63, 32) /* First stage context fields */ -#define RISCV_IOMMU_PC_FSC_PPN GENMASK_ULL(43, 0) +#define RISCV_IOMMU_PC_FSC_PPN RISCV_IOMMU_ATP_PPN_FIELD #define RISCV_IOMMU_PC_FSC_RESERVED GENMASK_ULL(59, 44) enum riscv_iommu_fq_ttypes { diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index d46beb2d64..76e0fcd873 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -1042,10 +1042,10 @@ static int riscv_iommu_ctx_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx) return RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT; } le64_to_cpus(&de); - if (!(de & RISCV_IOMMU_PC_TA_V)) { + if (!(de & RISCV_IOMMU_PDTE_VALID)) { return RISCV_IOMMU_FQ_CAUSE_PDT_INVALID; } - addr = PPN_PHYS(get_field(de, RISCV_IOMMU_PC_FSC_PPN)); + addr = PPN_PHYS(get_field(de, RISCV_IOMMU_PDTE_PPN)); } riscv_iommu_hpm_incr_ctr(s, ctx, RISCV_IOMMU_HPMEVENT_PD_WALK);
The PPN field in a non-leaf PDT entry is positioned differently from that in a leaf PDT entry. The original implementation incorrectly used the leaf entry's PPN mask to extract the PPN from a non-leaf entry, leading to an erroneous page table walk. This commit introduces new macros to properly define the fields for non-leaf PDT entries and corrects the page table walk. Signed-off-by: Jason Chien <jason.chien@sifive.com> --- hw/riscv/riscv-iommu-bits.h | 6 +++++- hw/riscv/riscv-iommu.c | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-)