| Message ID | 20250304064710.2128993-2-jamin_lin@aspeedtech.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Fix hw-strap for AST2700 | expand |
> Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning > is done, therefore skipping the u-boot-spl dram_init() process. > > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> > Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Nabih Estefan <nabihestefan@google.com> Thanks, Nabih > --- > hw/misc/aspeed_scu.c | 2 ++ > 1 file changed, 2 insertions(+) > diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c > index bac1441b06..50f74fbabd 100644 > --- a/hw/misc/aspeed_scu.c > +++ b/hw/misc/aspeed_scu.c > @@ -157,6 +157,7 @@ > #define AST2700_SCU_FREQ_CNTR TO_REG(0x3b0) > #define AST2700_SCU_CPU_SCRATCH_0 TO_REG(0x780) > #define AST2700_SCU_CPU_SCRATCH_1 TO_REG(0x784) > +#define AST2700_SCU_VGA_SCRATCH_0 TO_REG(0x900) > > #define AST2700_SCUIO_CLK_STOP_CTL_1 TO_REG(0x240) > #define AST2700_SCUIO_CLK_STOP_CLR_1 TO_REG(0x244) > @@ -930,6 +931,7 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = { > [AST2700_SCU_FREQ_CNTR] = 0x000375eb, > [AST2700_SCU_CPU_SCRATCH_0] = 0x00000000, > [AST2700_SCU_CPU_SCRATCH_1] = 0x00000004, > + [AST2700_SCU_VGA_SCRATCH_0] = 0x00000040, > }; > > static void aspeed_ast2700_scu_reset(DeviceState *dev) >
Nabih, On 3/6/25 01:04, Nabih Estefan wrote: >> Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning >> is done, therefore skipping the u-boot-spl dram_init() process. >> >> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> >> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> >> Reviewed-by: Cédric Le Goater <clg@redhat.com> > > Tested-by: Nabih Estefan <nabihestefan@google.com> Thanks for the feedback ! Can you tell us a bit more about your tests ? C.
Hi Cédric, We have a custom machine and a custom image using the AST27x0 A0. I ran some of our internal tests using these patches. They even fixed some of the errors we’d been seeing recently! I’m also working on testing through the A1 patches, will reply to those soon. Thanks, Nabih On Thu, Mar 6, 2025 at 12:05 AM Cédric Le Goater <clg@kaod.org> wrote: > > Nabih, > > On 3/6/25 01:04, Nabih Estefan wrote: > >> Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning > >> is done, therefore skipping the u-boot-spl dram_init() process. > >> > >> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> > >> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> > >> Reviewed-by: Cédric Le Goater <clg@redhat.com> > > > > Tested-by: Nabih Estefan <nabihestefan@google.com> > Thanks for the feedback ! > > Can you tell us a bit more about your tests ? > > > C. > >
Hello, On 3/6/25 19:05, Nabih Estefan wrote: > Hi Cédric, > > We have a custom machine and a custom image using the AST27x0 A0. I ran > some of our internal tests using these patches. They even fixed some of the > errors we’d been seeing recently! > > I’m also working on testing through the A1 patches, will reply to those soon. I pushed them on the aspeed-next branch. https://github.com/legoater/qemu/commits/aspeed-next/ and should send a PR around the week-end. Thanks, C.
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index bac1441b06..50f74fbabd 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -157,6 +157,7 @@ #define AST2700_SCU_FREQ_CNTR TO_REG(0x3b0) #define AST2700_SCU_CPU_SCRATCH_0 TO_REG(0x780) #define AST2700_SCU_CPU_SCRATCH_1 TO_REG(0x784) +#define AST2700_SCU_VGA_SCRATCH_0 TO_REG(0x900) #define AST2700_SCUIO_CLK_STOP_CTL_1 TO_REG(0x240) #define AST2700_SCUIO_CLK_STOP_CLR_1 TO_REG(0x244) @@ -930,6 +931,7 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = { [AST2700_SCU_FREQ_CNTR] = 0x000375eb, [AST2700_SCU_CPU_SCRATCH_0] = 0x00000000, [AST2700_SCU_CPU_SCRATCH_1] = 0x00000004, + [AST2700_SCU_VGA_SCRATCH_0] = 0x00000040, }; static void aspeed_ast2700_scu_reset(DeviceState *dev)