diff mbox series

[PULL,31/59] target/riscv: Fix the hpmevent mask

Message ID	20250305015307.1463560-32-alistair.francis@wdc.com (mailing list archive)
State	New
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Atish Patra <atishp@rivosinc.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL 31/59] target/riscv: Fix the hpmevent mask Date: Wed, 5 Mar 2025 11:52:39 +1000 Message-ID: <20250305015307.1463560-32-alistair.francis@wdc.com> In-Reply-To: <20250305015307.1463560-1-alistair.francis@wdc.com> References: <20250305015307.1463560-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() \| expand [PULL,01/59] target/riscv/csr.c: fix deadcode in rmw_xireg() [PULL,02/59] target/riscv/csr.c: fix 'ret' deadcode in rmw_xireg() [PULL,03/59] target/riscv/csr.c: fix deadcode in rmw_xiregi() [PULL,04/59] target/riscv/csr.c: fix deadcode in aia_smode32() [PULL,05/59] target/riscv/cpu_helper.c: fix bad_shift in riscv_cpu_interrupt() [PULL,06/59] target/riscv: rvv: Fix unexpected behavior of vector reduction instructions when vl is… [PULL,07/59] target/riscv: rvv: Fix incorrect vlen comparison in prop_vlen_set [PULL,08/59] target/riscv/debug.c: use wp size = 4 for 32-bit CPUs [PULL,09/59] target/riscv: throw debug exception before page fault [PULL,10/59] hw/intc/riscv_aplic: Remove redundant "hart_idx" masking [PULL,11/59] target/riscv: add ssu64xl [PULL,12/59] target/riscv: use RVB in RVA22U64 [PULL,13/59] target/riscv: add profile u_parent and s_parent [PULL,14/59] target/riscv: change priv_ver check in validate_profile() [PULL,15/59] target/riscv: add RVA23U64 profile [PULL,16/59] target/riscv: add RVA23S64 profile [PULL,17/59] hw/riscv/riscv-iommu: Remove redundant struct members [PULL,18/59] hw/riscv/riscv-iommu-bits: Remove duplicate definitions [PULL,19/59] goldfish_rtc: Fix tick_offset migration [PULL,20/59] hw/riscv/virt: Add serial alias in DTB [PULL,21/59] MAINTAINERS: Remove Bin Meng from RISC-V maintainers [PULL,22/59] target/riscv: Remove obsolete sfence.vm instruction [PULL,23/59] target/riscv: Add Control Transfer Records CSR definitions. [PULL,24/59] target/riscv: Add support for Control Transfer Records extension CSRs. [PULL,25/59] target/riscv: Add support to record CTR entries. [PULL,26/59] target/riscv: Add CTR sctrclr instruction. [PULL,27/59] target/riscv: machine: Add Control Transfer Record state description [PULL,28/59] target/riscv: log guest errors when reserved bits are set in PTEs [PULL,29/59] disas/riscv: Fix minor whitespace issues [PULL,30/59] disas/riscv: Add missing Sdtrig CSRs [PULL,31/59] target/riscv: Fix the hpmevent mask [PULL,32/59] target/riscv: Mask out upper sscofpmf bits during validation [PULL,33/59] target/riscv: remove warnings about Smdbltrp/Smrnmi being disabled [PULL,34/59] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs. [PULL,35/59] target/riscv: Respect mseccfg.RLB bit for TOR mode PMP entry [PULL,36/59] linux-headers: Update to Linux v6.14-rc3 [PULL,37/59] target/riscv/cpu.c: create flag for ziccrse [PULL,38/59] target/riscv/kvm: add extensions after 6.14-rc3 update [PULL,39/59] hw/riscv/riscv-iommu.h: add missing headers [PULL,40/59] hw/riscv/riscv-iommu-bits.h: HPM bits [PULL,41/59] hw/riscv/riscv-iommu: add riscv-iommu-hpm file [PULL,42/59] hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr() [PULL,43/59] hw/riscv/riscv-iommu: instantiate hpm_timer [PULL,44/59] hw/riscv/riscv-iommu: add IOCOUNTINH mmio writes [PULL,45/59] hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write [PULL,46/59] hw/riscv/riscv-iommu: add hpm events mmio write [PULL,47/59] hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap [PULL,48/59] hw/riscv: add IOMMU HPM trace events [PULL,49/59] docs/specs/riscv-iommu.rst: add HPM support info [PULL,50/59] target/riscv/kvm: Add some exts support [PULL,51/59] binfmt: Shuffle things around [PULL,52/59] binfmt: Normalize host CPU architecture [PULL,53/59] binfmt: Add --ignore-family option [PULL,54/59] hw/intc/imsic: refine the IMSIC realize [PULL,55/59] hw/intc/aplic: refine the APLIC realize [PULL,56/59] hw/intc/aplic: refine kvm_msicfgaddr [PULL,57/59] target/riscv/cpu: remove unneeded !kvm_enabled() check [PULL,58/59] target/riscv/kvm: add kvm_riscv_reset_regs_csr() [PULL,59/59] target/riscv/kvm: add missing KVM CSRs

Commit Message

Alistair Francis March 5, 2025, 1:52 a.m. UTC

From: Atish Patra <atishp@rivosinc.com>

As per the latest privilege specification v1.13[1], the sscofpmf
only reserves first 8 bits of hpmeventX. Update the corresponding
masks accordingly.

[1]https://github.com/riscv/riscv-isa-manual/issues/1578

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250206-pmu_minor_fixes-v2-1-1bb0f4aeb8b4@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff mbox series

Patch

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 70ef443c99..a30317c617 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -1078,9 +1078,8 @@  typedef enum CTRType {
                                             MHPMEVENTH_BIT_VSINH | \
                                             MHPMEVENTH_BIT_VUINH)
 
-#define MHPMEVENT_SSCOF_MASK               _ULL(0xFFFF000000000000)
-#define MHPMEVENT_IDX_MASK                 0xFFFFF
-#define MHPMEVENT_SSCOF_RESVD              16
+#define MHPMEVENT_SSCOF_MASK               MAKE_64BIT_MASK(63, 56)
+#define MHPMEVENT_IDX_MASK                 (~MHPMEVENT_SSCOF_MASK)
 
 /* RISC-V-specific interrupt pending bits. */
 #define CPU_INTERRUPT_RNMI                 CPU_INTERRUPT_TGT_EXT_0