| Message ID | 20250305102632.91376-1-santimonserr@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | docs/about/emulation: Fix broken link | expand |
On 05/03/2025 11.26, Santiago Monserrat Campanello wrote: > semihosting link to risc-v changed > > Signed-off-by: Santiago Monserrat Campanello <santimonserr@gmail.com> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717 > --- > the original one linked it's still accesible on > https://github.com/riscv-non-isa/riscv-semihosting/blob/0.2/riscv-semihosting-spec.adoc > --- > docs/about/emulation.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst > index 3bc3579434..a72591ee4d 100644 > --- a/docs/about/emulation.rst > +++ b/docs/about/emulation.rst > @@ -171,7 +171,7 @@ for that architecture. > - Unified Hosting Interface (MD01069) > * - RISC-V > - System and User-mode > - - https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc > + - https://github.com/riscv-non-isa/riscv-semihosting/blob/main/riscv-semihosting.adoc > * - Xtensa > - System > - Tensilica ISS SIMCALL Reviewed-by: Thomas Huth <thuth@redhat.com>
On Wed, Mar 5, 2025 at 8:27 PM Santiago Monserrat Campanello <santimonserr@gmail.com> wrote: > > semihosting link to risc-v changed > > Signed-off-by: Santiago Monserrat Campanello <santimonserr@gmail.com> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > the original one linked it's still accesible on > https://github.com/riscv-non-isa/riscv-semihosting/blob/0.2/riscv-semihosting-spec.adoc > --- > docs/about/emulation.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst > index 3bc3579434..a72591ee4d 100644 > --- a/docs/about/emulation.rst > +++ b/docs/about/emulation.rst > @@ -171,7 +171,7 @@ for that architecture. > - Unified Hosting Interface (MD01069) > * - RISC-V > - System and User-mode > - - https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc > + - https://github.com/riscv-non-isa/riscv-semihosting/blob/main/riscv-semihosting.adoc > * - Xtensa > - System > - Tensilica ISS SIMCALL > -- > 2.43.0 > >
On Wed, Mar 5, 2025 at 8:27 PM Santiago Monserrat Campanello <santimonserr@gmail.com> wrote: > > semihosting link to risc-v changed > > Signed-off-by: Santiago Monserrat Campanello <santimonserr@gmail.com> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717 Thanks! Applied to riscv-to-apply.next Alistair > --- > the original one linked it's still accesible on > https://github.com/riscv-non-isa/riscv-semihosting/blob/0.2/riscv-semihosting-spec.adoc > --- > docs/about/emulation.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst > index 3bc3579434..a72591ee4d 100644 > --- a/docs/about/emulation.rst > +++ b/docs/about/emulation.rst > @@ -171,7 +171,7 @@ for that architecture. > - Unified Hosting Interface (MD01069) > * - RISC-V > - System and User-mode > - - https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc > + - https://github.com/riscv-non-isa/riscv-semihosting/blob/main/riscv-semihosting.adoc > * - Xtensa > - System > - Tensilica ISS SIMCALL > -- > 2.43.0 > >
diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst index 3bc3579434..a72591ee4d 100644 --- a/docs/about/emulation.rst +++ b/docs/about/emulation.rst @@ -171,7 +171,7 @@ for that architecture. - Unified Hosting Interface (MD01069) * - RISC-V - System and User-mode - - https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc + - https://github.com/riscv-non-isa/riscv-semihosting/blob/main/riscv-semihosting.adoc * - Xtensa - System - Tensilica ISS SIMCALL
semihosting link to risc-v changed Signed-off-by: Santiago Monserrat Campanello <santimonserr@gmail.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717 --- the original one linked it's still accesible on https://github.com/riscv-non-isa/riscv-semihosting/blob/0.2/riscv-semihosting-spec.adoc --- docs/about/emulation.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)