diff mbox series

[PULL,47/54] target/sparc: Constify SPARCCPUClass::cpu_def

Message ID	20250306154737.70886-48-philmd@linaro.org (mailing list archive)
State	New
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 47/54] target/sparc: Constify SPARCCPUClass::cpu_def Date: Thu, 6 Mar 2025 16:47:29 +0100 Message-ID: <20250306154737.70886-48-philmd@linaro.org> In-Reply-To: <20250306154737.70886-1-philmd@linaro.org> References: <20250306154737.70886-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,01/54] qemu/compiler: Absorb 'clang-tsa.h' \| expand [PULL,01/54] qemu/compiler: Absorb 'clang-tsa.h' [PULL,02/54] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed [PULL,03/54] gdbstub: Check for TCG before calling tb_flush() [PULL,04/54] cpus: Cache CPUClass early in instance_init() handler [PULL,05/54] cpus: Keep default fields initialization in cpu_common_initfn() [PULL,06/54] accel/accel: Make TYPE_ACCEL abstract [PULL,07/54] accel/tcg: Remove pointless initialization of cflags_next_tb [PULL,08/54] accel/tcg: Build tcg_flags helpers as common code [PULL,09/54] accel/tcg: Restrict tlb_init() / destroy() to TCG [PULL,10/54] accel/tcg: Restrict 'icount_align_option' global to TCG [PULL,11/54] accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h' [PULL,12/54] accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h' [PULL,13/54] accel: Forward-declare AccelOpsClass in 'qemu/typedefs.h' [PULL,14/54] accel/accel-cpu-target.h: Include missing 'cpu.h' header [PULL,15/54] accel/tcg: Include missing bswap headers in user-exec.c [PULL,16/54] accel/tcg: Take mmap lock in the whole cpu_memory_rw_debug() function [PULL,17/54] accel/tcg: Avoid using lock_user() in cpu_memory_rw_debug() [PULL,18/54] accel/tcg: Move cpu_memory_rw_debug() user implementation to user-exec.c [PULL,19/54] accel/kvm: Remove unused 'system/cpus.h' header in kvm-cpus.h [PULL,20/54] cpus: Fix style in cpu-target.c [PULL,21/54] cpus: Restrict cpu_common_post_load() code to TCG [PULL,22/54] cpus: Have cpu_class_init_props() per user / system emulation [PULL,23/54] cpus: Have cpu_exec_initfn() per user / system emulation [PULL,24/54] cpus: Restrict cpu_get_memory_mapping() to system emulation [PULL,25/54] hw/core/generic-loader: Do not open-code cpu_set_pc() [PULL,26/54] target/microblaze: Explode MO_TExx -> MO_TE \| MO_xx [PULL,27/54] target/microblaze: Set MO_TE once in do_load() / do_store() [PULL,28/54] target/microblaze: Introduce mo_endian() helper [PULL,29/54] target/microblaze: Consider endianness while translating code [PULL,30/54] target/i386/hvf: Variable type fixup in decoder [PULL,31/54] target/openrisc: Call cpu_openrisc_clock_init() in cpu_realize() [PULL,32/54] target/hexagon: Ensure not being build on system emulation [PULL,33/54] target/rx: Ensure not being build on user emulation [PULL,34/54] target/tricore: Ensure not being build on user emulation [PULL,35/54] target/mips: Fix possible MSA int overflow [PULL,36/54] target: Set disassemble_info::endian value for little-endian targets [PULL,37/54] target: Set disassemble_info::endian value for big-endian targets [PULL,38/54] target/arm: Set disassemble_info::endian value in disas_set_info() [PULL,39/54] target/microblaze: Set disassemble_info::endian value in disas_set_info [PULL,40/54] target/mips: Set disassemble_info::endian value in disas_set_info() [PULL,41/54] target/ppc: Set disassemble_info::endian value in disas_set_info() [PULL,42/54] target/riscv: Set disassemble_info::endian value in disas_set_info() [PULL,43/54] target/sh4: Set disassemble_info::endian value in disas_set_info() [PULL,44/54] target/xtensa: Set disassemble_info::endian value in disas_set_info() [PULL,45/54] disas: Remove target_words_bigendian() call in initialize_debug_target() [PULL,46/54] target/i386: Constify X86CPUModel uses [PULL,47/54] target/sparc: Constify SPARCCPUClass::cpu_def [PULL,48/54] target/xtensa: Finalize config in xtensa_register_core() [PULL,49/54] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL [PULL,50/54] target/riscv: Convert misa_mxl_max using GLib macros [PULL,51/54] target/alpha: Do not mix exception flags and FPCR bits [PULL,52/54] target/i386: Mark WHPX APIC region as little-endian [PULL,53/54] system: Open-code qemu_init_arch_modules() using target_name() [PULL,54/54] include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition

Commit Message

Philippe Mathieu-Daudé March 6, 2025, 3:47 p.m. UTC

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210133134.90879-3-philmd@linaro.org>
---
 target/sparc/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index dda811503b5..462bcb6c0e6 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -574,7 +574,7 @@  struct SPARCCPUClass {
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
-    sparc_def_t *cpu_def;
+    const sparc_def_t *cpu_def;
 };
 
 #ifndef CONFIG_USER_ONLY