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Tsirkin" , Marcel Apfelbaum , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-arm@nongnu.org (open list:MCIMX7D SABRE / i...), Jason Chien Subject: [PATCH 2/4] hw/pci: Introduce an API to set PCI host downstream mr for IOMMU integration Date: Sat, 8 Mar 2025 04:39:35 +0800 Message-ID: <20250307203952.13871-3-jason.chien@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20250307203952.13871-1-jason.chien@sifive.com> References: <20250307203952.13871-1-jason.chien@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=jason.chien@sifive.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When an IOMMU detects that a PCI host has registered struct PCIIOMMUOps, it should call pci_setup_iommu_downstream_mr(), which invokes PCIIOMMUOps.set_downstream_mr() to configure the PCI host's downstream memory region, directing inbound transactions to the IOMMU. Signed-off-by: Jason Chien --- hw/pci/pci.c | 8 ++++++++ include/hw/pci/pci.h | 9 +++++++++ 2 files changed, 17 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 1d42847ef0..983290ef0b 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2858,6 +2858,14 @@ void pci_device_unset_iommu_device(PCIDevice *dev) } } +void pci_setup_iommu_downstream_mr(PCIBus *bus, MemoryRegion *mr) +{ + assert(bus->iommu_ops); + assert(bus->iommu_ops->set_downstream_mr); + + bus->iommu_ops->set_downstream_mr(bus->iommu_opaque, mr); +} + void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque) { /* diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index fcf648da19..1ad5dc7d9d 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -442,6 +442,15 @@ bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, Error **errp); void pci_device_unset_iommu_device(PCIDevice *dev); +/** + * pci_setup_iommu_downstream_mr: Designate a downstream memory region + * for a PCIBus + * + * @bus: the #PCIBus being updated. + * @mr: the designated memory region. + */ +void pci_setup_iommu_downstream_mr(PCIBus *bus, MemoryRegion *mr); + /** * pci_setup_iommu: Initialize specific IOMMU handlers for a PCIBus *