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Tsirkin" , Marcel Apfelbaum , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-arm@nongnu.org (open list:MCIMX7D SABRE / i...), Jason Chien Subject: [PATCH 4/4] hw/riscv/riscv-iommu: Connect the IOMMU with PCI hosts that have ATUs Date: Sat, 8 Mar 2025 04:39:37 +0800 Message-ID: <20250307203952.13871-5-jason.chien@sifive.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20250307203952.13871-1-jason.chien@sifive.com> References: <20250307203952.13871-1-jason.chien@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=jason.chien@sifive.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When the IOMMU detects that bus->iommu_ops has been registered, indicating the presence of an ATU, it sets the bus's downstream memory region to ensure transactions are directed to the IOMMU. Signed-off-by: Jason Chien Reviewed-by: Daniel Henrique Barboza --- hw/riscv/riscv-iommu.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index d46beb2d64..9701fe3831 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2628,11 +2628,16 @@ static const PCIIOMMUOps riscv_iommu_ops = { void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus, Error **errp) { - if (bus->iommu_ops && - bus->iommu_ops->get_address_space == riscv_iommu_find_as) { - /* Allow multiple IOMMUs on the same PCIe bus, link known devices */ - RISCVIOMMUState *last = (RISCVIOMMUState *)bus->iommu_opaque; - QLIST_INSERT_AFTER(last, iommu, iommus); + if (bus->iommu_ops) { + if (bus->iommu_ops->get_address_space == riscv_iommu_find_as) { + /* Allow multiple IOMMUs on the same PCIe bus, link known devices */ + RISCVIOMMUState *last = (RISCVIOMMUState *)bus->iommu_opaque; + QLIST_INSERT_AFTER(last, iommu, iommus); + } else { + /* The bus has an ATU. Set its downsteam memory region. */ + AddressSpace *as = riscv_iommu_space(iommu, 0); + pci_setup_iommu_downstream_mr(bus, as->root); + } } else if (!bus->iommu_ops && !bus->iommu_opaque) { pci_setup_iommu(bus, &riscv_iommu_ops, iommu); } else {