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([38.39.164.180]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736d2ae318csm1708308b3a.53.2025.03.09.21.58.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 21:58:51 -0700 (PDT) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Alistair Francis , Richard Henderson , Harsh Prateek Bora , alex.bennee@linaro.org, Palmer Dabbelt , Daniel Henrique Barboza , kvm@vger.kernel.org, Peter Xu , Nicholas Piggin , Liu Zhiwei , David Hildenbrand , Weiwei Li , Paul Durrant , "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anthony PERARD , Yoshinori Sato , manos.pitsidianakis@linaro.org, qemu-riscv@nongnu.org, Paolo Bonzini , xen-devel@lists.xenproject.org, Stefano Stabellini , Pierrick Bouvier Subject: [PATCH 02/16] exec/memory_ldst_phys: extract memory_ldst_phys declarations from cpu-all.h Date: Sun, 9 Mar 2025 21:58:28 -0700 Message-Id: <20250310045842.2650784-3-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250310045842.2650784-1-pierrick.bouvier@linaro.org> References: <20250310045842.2650784-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org They are now accessible through exec/memory.h instead, and we make sure all variants are available for common or target dependent code. To allow this, we need to implement address_space_st{*}_cached, simply forwarding the calls to _cached_slow variants. Signed-off-by: Pierrick Bouvier --- include/exec/cpu-all.h | 15 ------------ include/exec/memory.h | 36 +++++++++++++++++++++++++++++ include/exec/memory_ldst_phys.h.inc | 5 +--- 3 files changed, 37 insertions(+), 19 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 17ea82518a0..1c2e18f492b 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -75,21 +75,6 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val MEMTXATTRS_UNSPECIFIED, NULL); } -#define SUFFIX -#define ARG1 as -#define ARG1_DECL AddressSpace *as -#define TARGET_ENDIANNESS -#include "exec/memory_ldst_phys.h.inc" - -/* Inline fast path for direct RAM access. */ -#define ENDIANNESS -#include "exec/memory_ldst_cached.h.inc" - -#define SUFFIX _cached -#define ARG1 cache -#define ARG1_DECL MemoryRegionCache *cache -#define TARGET_ENDIANNESS -#include "exec/memory_ldst_phys.h.inc" #endif /* page related stuff */ diff --git a/include/exec/memory.h b/include/exec/memory.h index 78c4e0aec8d..7c20f36a312 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -2798,6 +2798,42 @@ static inline void address_space_stb_cached(MemoryRegionCache *cache, } } +static inline uint16_t address_space_lduw_cached(MemoryRegionCache *cache, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_lduw_cached_slow(cache, addr, attrs, result); +} + +static inline void address_space_stw_cached(MemoryRegionCache *cache, + hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stw_cached_slow(cache, addr, val, attrs, result); +} + +static inline uint32_t address_space_ldl_cached(MemoryRegionCache *cache, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_ldl_cached_slow(cache, addr, attrs, result); +} + +static inline void address_space_stl_cached(MemoryRegionCache *cache, + hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stl_cached_slow(cache, addr, val, attrs, result); +} + +static inline uint64_t address_space_ldq_cached(MemoryRegionCache *cache, + hwaddr addr, MemTxAttrs attrs, MemTxResult *result) +{ + return address_space_ldq_cached_slow(cache, addr, attrs, result); +} + +static inline void address_space_stq_cached(MemoryRegionCache *cache, + hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result) +{ + address_space_stq_cached_slow(cache, addr, val, attrs, result); +} + #define ENDIANNESS _le #include "exec/memory_ldst_cached.h.inc" diff --git a/include/exec/memory_ldst_phys.h.inc b/include/exec/memory_ldst_phys.h.inc index ecd678610d1..db67de75251 100644 --- a/include/exec/memory_ldst_phys.h.inc +++ b/include/exec/memory_ldst_phys.h.inc @@ -19,7 +19,6 @@ * License along with this library; if not, see . */ -#ifdef TARGET_ENDIANNESS static inline uint16_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr) { return glue(address_space_lduw, SUFFIX)(ARG1, addr, @@ -55,7 +54,7 @@ static inline void glue(stq_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val) glue(address_space_stq, SUFFIX)(ARG1, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } -#else + static inline uint8_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr) { return glue(address_space_ldub, SUFFIX)(ARG1, addr, @@ -139,9 +138,7 @@ static inline void glue(stq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t va glue(address_space_stq_be, SUFFIX)(ARG1, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } -#endif #undef ARG1_DECL #undef ARG1 #undef SUFFIX -#undef TARGET_ENDIANNESS