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[PULL,03/72] hw/ppc: Deprecate 405 CPUs

Message ID	20250311125815.903177-4-npiggin@gmail.com (mailing list archive)
State	New
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Nicholas Piggin <npiggin@gmail.com> To: qemu-devel@nongnu.org Cc: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org, =?utf-8?q?C?= =?utf-8?q?=C3=A9dric_Le_Goater?= <clg@redhat.com> Subject: [PULL 03/72] hw/ppc: Deprecate 405 CPUs Date: Tue, 11 Mar 2025 22:56:57 +1000 Message-ID: <20250311125815.903177-4-npiggin@gmail.com> In-Reply-To: <20250311125815.903177-1-npiggin@gmail.com> References: <20250311125815.903177-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=npiggin@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,01/72] ppc/ppc405: Remove tests \| expand [PULL,01/72] ppc/ppc405: Remove tests [PULL,02/72] ppc/ppc405: Remove boards [PULL,03/72] hw/ppc: Deprecate 405 CPUs [PULL,05/72] pseries: Update SLOF firmware image [PULL,06/72] ppc/pnv/phb4: Add pervasive chiplet support to PHB4/5 [PULL,07/72] ppc/pnv/homer: Fix OCC registers [PULL,08/72] ppc/pnv/homer: Make dummy reads return 0 [PULL,09/72] ppc/pnv/occ: Fix common area sensor offsets [PULL,10/72] ppc/pnv/homer: class-based base and size [PULL,11/72] ppc/pnv/occ: Better document OCCMISC bits [PULL,12/72] ppc/pnv: Make HOMER memory a RAM region [PULL,13/72] ppc/pnv/occ: Update pstate frequency tables [PULL,14/72] ppc/pnv/occ: Add POWER10 OCC-OPAL data format [PULL,15/72] ppc/pnv/occ: Implement a basic dynamic OCC model [PULL,16/72] target/ppc: Add Power9/10 power management SPRs [PULL,17/72] ppc/pnv: Support LPC host controller irqs other than serirqs [PULL,18/72] ppc/pnv: raise no-response errors if an LPC transaction fails [PULL,19/72] ppc/pnv: Implement LPC FW address space IDSEL [PULL,20/72] ppc/pnv: Move PNOR to offset 0 in the ISA FW space [PULL,21/72] ppc/pnv: Add a PNOR address and size sanity checks [PULL,22/72] ppc/pnv: Add a default formatted PNOR image [PULL,23/72] ppc/xive2: Update NVP save/restore for group attributes [PULL,24/72] ppc/xive: Rename ipb_to_pipr() to xive_ipb_to_pipr() [PULL,25/72] ppc/xive2: Add grouping level to notification [PULL,26/72] ppc/xive2: Support group-matching when looking for target [PULL,27/72] ppc/xive2: Add undelivered group interrupt to backlog [PULL,28/72] ppc/xive2: Process group backlog when pushing an OS context [PULL,29/72] ppc/xive2: Process group backlog when updating the CPPR [PULL,30/72] qtest/xive: Add group-interrupt test [PULL,31/72] ppc/xive2: Add support for MMIO operations on the NVPG/NVC BAR [PULL,32/72] ppc/xive2: Support crowd-matching when looking for target [PULL,33/72] pnv/xive2: Rename nvp_ to nvx_ if they can refer to NVP or NVGC [PULL,34/72] ppc/xive2: Check crowd backlog when scanning group backlog [PULL,35/72] qtest/xive: Change printf to g_test_message [PULL,36/72] qtest/xive: Add test of pool interrupts [PULL,37/72] hw/ssi/pnv_spi: Replace PnvXferBuffer with Fifo8 structure [PULL,38/72] hw/ssi/pnv_spi: Use local var seq_index instead of get_seq_index(). [PULL,39/72] hw/ssi/pnv_spi: Make bus names distinct for each controllers of a socket [PULL,40/72] hw/ssi/pnv_spi: Put a limit to RDR match failures [PULL,41/72] hw/ppc/spapr: Restrict CONFER hypercall to TCG [PULL,42/72] ppc/pnv: Add new PowerPC Special Purpose Registers (RWMR) [PULL,43/72] target/ppc: Make ppc_ldl_code() declaration public [PULL,44/72] target/ppc: Move TCG specific exception handlers to tcg-excp_helper.c [PULL,45/72] target/ppc: Move ppc_ldl_code() to tcg-excp_helper.c [PULL,46/72] target/ppc: Ensure powerpc_mcheck_checkstop() is only called under TCG [PULL,47/72] target/ppc: Restrict powerpc_checkstop() to TCG [PULL,48/72] target/ppc: Remove raise_exception_ra() [PULL,49/72] target/ppc: Restrict exception helpers to TCG [PULL,50/72] target/ppc: Restrict various common helpers to TCG [PULL,51/72] target/ppc: Fix style in excp_helper.c [PULL,52/72] target/ppc: Make powerpc_excp() prototype public [PULL,53/72] target/ppc: Restrict ATTN / SCV / PMINSN helpers to TCG [PULL,54/72] hw/ppc/spapr: Convert HPTE() macro as hpte_get_ptr() method [PULL,55/72] hw/ppc/spapr: Convert HPTE_VALID() macro as hpte_is_valid() method [PULL,56/72] hw/ppc/spapr: Convert HPTE_DIRTY() macro as hpte_is_dirty() method [PULL,57/72] hw/ppc/spapr: Convert CLEAN_HPTE() macro as hpte_set_clean() method [PULL,58/72] hw/ppc/spapr: Convert DIRTY_HPTE() macro as hpte_set_dirty() method [PULL,59/72] hw/ppc/epapr: Do not swap ePAPR magic value [PULL,60/72] ppc: Enable 2nd DAWR support on Power10 PowerNV machine [PULL,61/72] ppc: spapr: Enable 2nd DAWR on Power10 pSeries machine [PULL,62/72] spapr: nested: Add support for reporting Hostwide state counter [PULL,63/72] target/ppc: fix timebase register reset state [PULL,64/72] target/ppc: Wire up BookE ATB registers for e500 family [PULL,65/72] target/ppc: Avoid warning message for zero process table entries [PULL,66/72] spapr: Generate random HASHPKEYR for spapr machines [PULL,67/72] ppc/amigaone: Simplify replacement dummy_fw [PULL,68/72] ppc/amigaone: Implement NVRAM emulation [PULL,69/72] ppc/amigaone: Add default environment [PULL,70/72] ppc/amigaone: Add kernel and initrd support [PULL,71/72] ppc/amigaone: Add #defines for memory map constants [PULL,72/72] docs/system/ppc/amigang.rst: Update for NVRAM emulation

Commit Message

Nicholas Piggin March 11, 2025, 12:56 p.m. UTC

From: Cédric Le Goater <clg@redhat.com>

The ref405ep machine is scheduled for removal in QEMU 10.0. Keep the
405 CPU implementation for a while because it is theoretically
possible to model the power management (OCC) co-processor found on the
IBM POWER [8-11] processors.

Signed-off-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20250204080649.836155-4-clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 docs/about/deprecated.rst | 9 +++++++++
 1 file changed, 9 insertions(+)

diff mbox series

Patch

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 3d39d2a9da..e2b4f077d4 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -266,6 +266,15 @@  in the QEMU object model anymore. ``Sun-UltraSparc-IIIi+`` and
 but for consistency these will get removed in a future release, too.
 Use ``Sun-UltraSparc-IIIi-plus`` and ``Sun-UltraSparc-IV-plus`` instead.
 
+PPC 405 CPUs (since 10.0)
+'''''''''''''''''''''''''
+
+The PPC 405 CPU has no known users and the ``ref405ep`` machine was
+removed in QEMU 10.0. Since the IBM POWER [8-11] processors uses an
+embedded 405 for power management (OCC) and other internal tasks, it
+is theoretically possible to use QEMU to model them. Let's keep the
+CPU implementation for a while before removing all support.
+
 System emulator machines
 ------------------------