From patchwork Tue Mar 11 14:10:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 14011939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCA75C28B30 for ; Tue, 11 Mar 2025 14:13:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ts0Ly-0002PV-94; Tue, 11 Mar 2025 10:13:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0Lq-0001z4-BO; Tue, 11 Mar 2025 10:13:01 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ts0Lo-0006za-Ln; Tue, 11 Mar 2025 10:12:58 -0400 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ZBwdT5Y4pz6D8cG; Tue, 11 Mar 2025 22:10:21 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 5D7DC140B63; Tue, 11 Mar 2025 22:12:54 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 11 Mar 2025 15:12:46 +0100 To: , CC: , , , , , , , , , , , , , Subject: [RFC PATCH v2 07/20] hw/arm/smmu-common: Introduce callbacks for PCIIOMMUOps Date: Tue, 11 Mar 2025 14:10:32 +0000 Message-ID: <20250311141045.66620-8-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum X-Patchwork-Original-From: Shameer Kolothum via From: Shameerali Kolothum Thodi Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Subsequently smmuv3-accel will provide these callbacks Signed-off-by: Shameer Kolothum --- hw/arm/smmu-common.c | 27 +++++++++++++++++++++++++++ include/hw/arm/smmu-common.h | 5 +++++ 2 files changed, 32 insertions(+) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 83c0693f5a..9fd455baa0 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -865,6 +865,10 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) SMMUState *s = opaque; SMMUPciBus *sbus = smmu_get_sbus(s, bus); + if (s->accel && s->get_address_space) { + return s->get_address_space(bus, opaque, devfn); + } + sdev = sbus->pbdev[devfn]; if (!sdev) { sdev = sbus->pbdev[devfn] = g_new0(SMMUDevice, 1); @@ -874,8 +878,31 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) return &sdev->as; } +static bool smmu_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, + HostIOMMUDevice *hiod, Error **errp) +{ + SMMUState *s = opaque; + + if (s->accel && s->set_iommu_device) { + return s->set_iommu_device(bus, opaque, devfn, hiod, errp); + } + + return false; +} + +static void smmu_dev_unset_iommu_device(PCIBus *bus, void *opaque, int devfn) +{ + SMMUState *s = opaque; + + if (s->accel && s->unset_iommu_device) { + s->unset_iommu_device(bus, opaque, devfn); + } +} + static const PCIIOMMUOps smmu_ops = { .get_address_space = smmu_find_add_as, + .set_iommu_device = smmu_dev_set_iommu_device, + .unset_iommu_device = smmu_dev_unset_iommu_device, }; SMMUDevice *smmu_find_sdev(SMMUState *s, uint32_t sid) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 80ff2ef6aa..7b05640167 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -160,6 +160,11 @@ struct SMMUState { /* For smmuv3-accel */ bool accel; + + AddressSpace * (*get_address_space)(PCIBus *bus, void *opaque, int devfn); + bool (*set_iommu_device)(PCIBus *bus, void *opaque, int devfn, + HostIOMMUDevice *dev, Error **errp); + void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn); }; struct SMMUBaseClass {