| Message ID | 20250317065938.1902272-1-troy_lee@aspeedtech.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [1/2] aspeed: Fix maximum number of spi controller | expand |
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index f899356ed9..f069d17d16 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -42,7 +42,7 @@ #include "hw/char/serial-mm.h" #include "hw/intc/arm_gicv3.h" -#define ASPEED_SPIS_NUM 2 +#define ASPEED_SPIS_NUM 3 #define ASPEED_EHCIS_NUM 2 #define ASPEED_WDTS_NUM 8 #define ASPEED_CPUS_NUM 4
Commit 6de4aa8dc544 ("hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1") extends ast2700a1 spis_num to 3, but ASPEED_SPIS_NUM defines the maximum number of spi controller to 2, result in ehci[0] is being overwritten in runtime. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> --- include/hw/arm/aspeed_soc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)