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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1fe60ad4sm107914985e9.29.2025.03.17.07.28.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 07:28:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-10.1 3/9] target/arm: Handle AArch64 in TYPE_ARM_CPU gdb_arch_name Date: Mon, 17 Mar 2025 14:28:13 +0000 Message-ID: <20250317142819.900029-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250317142819.900029-1-peter.maydell@linaro.org> References: <20250317142819.900029-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of having the TYPE_AARCH64_CPU subclass set CPUClass::gdb_arch_name to a different function, make the TYPE_ARM_CPU implementation of the method handle AArch64. For the moment we make the "is this AArch64?" function test "is the CPU of TYPE_AARCH64_CPU?", so that this produces no behavioural change. When we've moved all the gdbstub related methods across to the base class, we will be able to change this to be "does the CPU have the ARM_FEATURE_AARCH64 feature?". Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 6 ++++++ target/arm/cpu.c | 3 +++ target/arm/cpu64.c | 6 ------ 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index bb962389192..a14c269fa5a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1691,6 +1691,12 @@ void aarch64_add_sve_properties(Object *obj); void aarch64_add_sme_properties(Object *obj); #endif +/* Return true if the gdbstub is presenting an AArch64 CPU */ +static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu) +{ + return object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU); +} + /* Read the CONTROL register as the MRS instruction would. */ uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 01786ac7879..d69403fda90 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2647,6 +2647,9 @@ static const gchar *arm_gdb_arch_name(CPUState *cs) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + if (arm_gdbstub_is_aarch64(cpu)) { + return "aarch64"; + } if (arm_feature(env, ARM_FEATURE_IWMMXT)) { return "iwmmxt"; } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8188ede5cc8..020b32f21e9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -813,11 +813,6 @@ static void aarch64_cpu_finalizefn(Object *obj) { } -static const gchar *aarch64_gdb_arch_name(CPUState *cs) -{ - return "aarch64"; -} - static void aarch64_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); @@ -825,7 +820,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = aarch64_cpu_gdb_read_register; cc->gdb_write_register = aarch64_cpu_gdb_write_register; cc->gdb_core_xml_file = "aarch64-core.xml"; - cc->gdb_arch_name = aarch64_gdb_arch_name; object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, aarch64_cpu_set_aarch64);