@@ -50,9 +50,11 @@ struct AspeedSgList {
struct AspeedMasks {
uint32_t src;
uint32_t dest;
+ uint32_t key;
uint32_t len;
uint32_t src_hi;
uint32_t dest_hi;
+ uint32_t key_hi;
};
void aspeed_test_md5(const char *machine, const uint32_t base,
@@ -591,6 +591,8 @@ void aspeed_test_addresses(const char *machine, const uint32_t base,
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 0);
+ g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==, 0);
+ g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0);
/* Check that the address masking is correct */
@@ -609,6 +611,14 @@ void aspeed_test_addresses(const char *machine, const uint32_t base,
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==,
expected->dest_hi);
+ qtest_writel(s, base + HACE_HASH_KEY_BUFF, 0xffffffff);
+ g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==,
+ expected->key);
+
+ qtest_writel(s, base + HACE_HASH_KEY_BUFF_HI, 0xffffffff);
+ g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==,
+ expected->key_hi);
+
qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==,
expected->len);
@@ -618,6 +628,8 @@ void aspeed_test_addresses(const char *machine, const uint32_t base,
qtest_writel(s, base + HACE_HASH_SRC_HI, 0);
qtest_writel(s, base + HACE_HASH_DIGEST, 0);
qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0);
+ qtest_writel(s, base + HACE_HASH_KEY_BUFF, 0);
+ qtest_writel(s, base + HACE_HASH_KEY_BUFF_HI, 0);
qtest_writel(s, base + HACE_HASH_DATA_LEN, 0);
/* Check that all bits are now zero */
@@ -625,6 +637,8 @@ void aspeed_test_addresses(const char *machine, const uint32_t base,
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 0);
+ g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==, 0);
+ g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0);
qtest_quit(s);
@@ -13,24 +13,28 @@
static const struct AspeedMasks ast1030_masks = {
.src = 0x7fffffff,
.dest = 0x7ffffff8,
+ .key = 0x7ffffff8,
.len = 0x0fffffff,
};
static const struct AspeedMasks ast2600_masks = {
.src = 0x7fffffff,
.dest = 0x7ffffff8,
+ .key = 0x7ffffff8,
.len = 0x0fffffff,
};
static const struct AspeedMasks ast2500_masks = {
.src = 0x3fffffff,
.dest = 0x3ffffff8,
+ .key = 0x3fffffc0,
.len = 0x0fffffff,
};
static const struct AspeedMasks ast2400_masks = {
.src = 0x0fffffff,
.dest = 0x0ffffff8,
+ .key = 0x0fffffc0,
.len = 0x0fffffff,
};
Added "key" and "key_hi" fields to "AspeedMasks" for 64-bit addresses test. Updated "aspeed_test_addresses" to validate "HACE_HASH_KEY_BUFF" and "HACE_HASH_KEY_BUFF_HI". Ensured correct masking of 64-bit addresses by checking both lower and upper 32-bit registers. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- tests/qtest/aspeed-hace-utils.h | 2 ++ tests/qtest/aspeed-hace-utils.c | 14 ++++++++++++++ tests/qtest/aspeed_hace-test.c | 4 ++++ 3 files changed, 20 insertions(+)