| Message ID | 20250323063404.13206-1-hemanshu.khilari.foss@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] docs/specs/riscv-iommu: Fixed broken link to external risv iommu document | expand |
On Sun, Mar 23, 2025 at 4:36 PM hemanshu.khilari.foss <hemanshu.khilari.foss@gmail.com> wrote: > > The links to riscv iommu specification document are incorrect. This patch > updates all the said link to point to correct location. > > Cc: qemu-riscv@nongnu.org > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2808 > Signed-off-by: hemanshu.khilari.foss <hemanshu.khilari.foss@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > docs/specs/riscv-iommu.rst | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst > index 000c7e1f57..991d376fdc 100644 > --- a/docs/specs/riscv-iommu.rst > +++ b/docs/specs/riscv-iommu.rst > @@ -4,7 +4,7 @@ RISC-V IOMMU support for RISC-V machines > ======================================== > > QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec > -version 1.0 `iommu1.0`_. > +version 1.0 `iommu1.0.0`_. > > The emulation includes a PCI reference device (riscv-iommu-pci) and a platform > bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt' > @@ -14,7 +14,7 @@ riscv-iommu-pci reference device > -------------------------------- > > This device implements the RISC-V IOMMU emulation as recommended by the section > -"Integrating an IOMMU as a PCIe device" of `iommu1.0`_: a PCI device with base > +"Integrating an IOMMU as a PCIe device" of `iommu1.0.0`_: a PCI device with base > class 08h, sub-class 06h and programming interface 00h. > > As a reference device it doesn't implement anything outside of the specification, > @@ -109,7 +109,7 @@ riscv-iommu options: > - "s-stage": enabled > - "g-stage": enabled > > -.. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf > +.. _iommu1.0.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0.0/riscv-iommu.pdf > > .. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivosinc.com/ > > -- > 2.42.0 > >
On Sun, Mar 23, 2025 at 4:36 PM hemanshu.khilari.foss <hemanshu.khilari.foss@gmail.com> wrote: > > The links to riscv iommu specification document are incorrect. This patch > updates all the said link to point to correct location. > > Cc: qemu-riscv@nongnu.org > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2808 > Signed-off-by: hemanshu.khilari.foss <hemanshu.khilari.foss@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > docs/specs/riscv-iommu.rst | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst > index 000c7e1f57..991d376fdc 100644 > --- a/docs/specs/riscv-iommu.rst > +++ b/docs/specs/riscv-iommu.rst > @@ -4,7 +4,7 @@ RISC-V IOMMU support for RISC-V machines > ======================================== > > QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec > -version 1.0 `iommu1.0`_. > +version 1.0 `iommu1.0.0`_. > > The emulation includes a PCI reference device (riscv-iommu-pci) and a platform > bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt' > @@ -14,7 +14,7 @@ riscv-iommu-pci reference device > -------------------------------- > > This device implements the RISC-V IOMMU emulation as recommended by the section > -"Integrating an IOMMU as a PCIe device" of `iommu1.0`_: a PCI device with base > +"Integrating an IOMMU as a PCIe device" of `iommu1.0.0`_: a PCI device with base > class 08h, sub-class 06h and programming interface 00h. > > As a reference device it doesn't implement anything outside of the specification, > @@ -109,7 +109,7 @@ riscv-iommu options: > - "s-stage": enabled > - "g-stage": enabled > > -.. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf > +.. _iommu1.0.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0.0/riscv-iommu.pdf > > .. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivosinc.com/ > > -- > 2.42.0 > >
diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst index 000c7e1f57..991d376fdc 100644 --- a/docs/specs/riscv-iommu.rst +++ b/docs/specs/riscv-iommu.rst @@ -4,7 +4,7 @@ RISC-V IOMMU support for RISC-V machines ======================================== QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec -version 1.0 `iommu1.0`_. +version 1.0 `iommu1.0.0`_. The emulation includes a PCI reference device (riscv-iommu-pci) and a platform bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt' @@ -14,7 +14,7 @@ riscv-iommu-pci reference device -------------------------------- This device implements the RISC-V IOMMU emulation as recommended by the section -"Integrating an IOMMU as a PCIe device" of `iommu1.0`_: a PCI device with base +"Integrating an IOMMU as a PCIe device" of `iommu1.0.0`_: a PCI device with base class 08h, sub-class 06h and programming interface 00h. As a reference device it doesn't implement anything outside of the specification, @@ -109,7 +109,7 @@ riscv-iommu options: - "s-stage": enabled - "g-stage": enabled -.. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf +.. _iommu1.0.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0.0/riscv-iommu.pdf .. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivosinc.com/
The links to riscv iommu specification document are incorrect. This patch updates all the said link to point to correct location. Cc: qemu-riscv@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2808 Signed-off-by: hemanshu.khilari.foss <hemanshu.khilari.foss@gmail.com> --- docs/specs/riscv-iommu.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)