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[RFC] target/arm: add bounding a->imm assertion

Message ID 20250325101752.58825-1-abelova@astralinux.ru (mailing list archive)
State New
Headers show
Series [RFC] target/arm: add bounding a->imm assertion | expand

Commit Message

Anastasia Belova March 25, 2025, 10:17 a.m. UTC
From: Anastasia Belova <nabelova31@gmail.com>

Add an assertion similar to that in the do_shr_narrow().
This will make sure that functions from sshll_ops
have correct arguments.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
---
 target/arm/tcg/translate-sve.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Anastasia Belova March 25, 2025, 10:20 a.m. UTC | #1
Sorry for accidentaly sending this patch twice.

My mail system reports that it can't be delivered to Peter Maydell 
<peter.maydell@linaro.org>
and I am trying to solve it.

On 3/25/25 1:17 PM, Anastasia Belova wrote:
> From: Anastasia Belova <nabelova31@gmail.com>
>
> Add an assertion similar to that in the do_shr_narrow().
> This will make sure that functions from sshll_ops
> have correct arguments.
>
> Found by Linux Verification Center (linuxtesting.org) with SVACE.
>
> Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
> ---
>   target/arm/tcg/translate-sve.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
> index d23be477b4..47ada85c92 100644
> --- a/target/arm/tcg/translate-sve.c
> +++ b/target/arm/tcg/translate-sve.c
> @@ -6250,6 +6250,7 @@ static bool do_shll_tb(DisasContext *s, arg_rri_esz *a,
>       if (a->esz < 0 || a->esz > 2) {
>           return false;
>       }
> +    assert(a->imm > 0 && a->imm <= (8 << a->esz));
>       if (sve_access_check(s)) {
>           unsigned vsz = vec_full_reg_size(s);
>           tcg_gen_gvec_2i(vec_full_reg_offset(s, a->rd),
diff mbox series

Patch

diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index d23be477b4..47ada85c92 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -6250,6 +6250,7 @@  static bool do_shll_tb(DisasContext *s, arg_rri_esz *a,
     if (a->esz < 0 || a->esz > 2) {
         return false;
     }
+    assert(a->imm > 0 && a->imm <= (8 << a->esz));
     if (sve_access_check(s)) {
         unsigned vsz = vec_full_reg_size(s);
         tcg_gen_gvec_2i(vec_full_reg_offset(s, a->rd),