Message ID | 20250402210328.52897-5-philmd@linaro.org (mailing list archive) |
---|---|
State | New |
Headers | show
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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b6656afsm17751785f8f.40.2025.04.02.14.03.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Apr 2025 14:03:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org Subject: [PATCH-for-10.1 04/43] accel/tcg: Introduce TCGCPUOps::mmu_index() callback Date: Wed, 2 Apr 2025 23:02:49 +0200 Message-ID: <20250402210328.52897-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250402210328.52897-1-philmd@linaro.org> References: <20250402210328.52897-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org |
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diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index f60e5303f21..106a0688da8 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -67,6 +67,9 @@ struct TCGCPUOps { /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); + /** @mmu_index: Callback for choosing softmmu mmu index */ + int (*mmu_index)(CPUState *cpu, bool ifetch); + #ifdef CONFIG_USER_ONLY /** * @fake_user_interrupt: Callback for 'fake exception' handling. diff --git a/include/exec/cpu-mmu-index.h b/include/exec/cpu-mmu-index.h index cfc13d46bea..651526e9f97 100644 --- a/include/exec/cpu-mmu-index.h +++ b/include/exec/cpu-mmu-index.h @@ -10,6 +10,7 @@ #define EXEC_CPU_MMU_INDEX_H #include "hw/core/cpu.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/debug-assert.h" #ifdef COMPILING_PER_TARGET #include "cpu.h" @@ -31,7 +32,9 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch) # endif #endif - int ret = cs->cc->mmu_index(cs, ifetch); + const TCGCPUOps *tcg_ops = cs->cc->tcg_ops; + int ret = tcg_ops->mmu_index ? tcg_ops->mmu_index(cs, ifetch) + : cs->cc->mmu_index(cs, ifetch); tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES); return ret; }