| Message ID | 20250403154956.791976-1-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | target/hexagon: Implement CPUState.mmu_index | expand |
On 3/4/25 17:49, Richard Henderson wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/hexagon/cpu.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c > index 766b678651..59fc9ed698 100644 > --- a/target/hexagon/cpu.c > +++ b/target/hexagon/cpu.c > @@ -313,6 +313,11 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp) > mcc->parent_realize(dev, errp); > } > > +static int hexagon_cpu_mmu_index(CPUState *cs, bool ifetch) > +{ > + return MMU_USER_IDX; Easy ;) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> > +} > + > static void hexagon_cpu_init(Object *obj) > { > } > @@ -341,6 +346,7 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data) > &mcc->parent_phases); > > cc->class_by_name = hexagon_cpu_class_by_name; > + cc->mmu_index = hexagon_cpu_mmu_index; > cc->dump_state = hexagon_dump_state; > cc->set_pc = hexagon_cpu_set_pc; > cc->get_pc = hexagon_cpu_get_pc;
On 4/3/25 08:49, Richard Henderson wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/hexagon/cpu.c | 6 ++++++ > 1 file changed, 6 insertions(+) I meant to add, this is to enable some of the other single-binary cleanups, wherein implementation of CPUState.mmu_index becomes mandatory. r~ > > diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c > index 766b678651..59fc9ed698 100644 > --- a/target/hexagon/cpu.c > +++ b/target/hexagon/cpu.c > @@ -313,6 +313,11 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp) > mcc->parent_realize(dev, errp); > } > > +static int hexagon_cpu_mmu_index(CPUState *cs, bool ifetch) > +{ > + return MMU_USER_IDX; > +} > + > static void hexagon_cpu_init(Object *obj) > { > } > @@ -341,6 +346,7 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data) > &mcc->parent_phases); > > cc->class_by_name = hexagon_cpu_class_by_name; > + cc->mmu_index = hexagon_cpu_mmu_index; > cc->dump_state = hexagon_dump_state; > cc->set_pc = hexagon_cpu_set_pc; > cc->get_pc = hexagon_cpu_get_pc;
On 4/3/2025 10:49 AM, Richard Henderson wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> > target/hexagon/cpu.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c > index 766b678651..59fc9ed698 100644 > --- a/target/hexagon/cpu.c > +++ b/target/hexagon/cpu.c > @@ -313,6 +313,11 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp) > mcc->parent_realize(dev, errp); > } > > +static int hexagon_cpu_mmu_index(CPUState *cs, bool ifetch) > +{ > + return MMU_USER_IDX; > +} > + > static void hexagon_cpu_init(Object *obj) > { > } > @@ -341,6 +346,7 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data) > &mcc->parent_phases); > > cc->class_by_name = hexagon_cpu_class_by_name; > + cc->mmu_index = hexagon_cpu_mmu_index; > cc->dump_state = hexagon_dump_state; > cc->set_pc = hexagon_cpu_set_pc; > cc->get_pc = hexagon_cpu_get_pc;
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 766b678651..59fc9ed698 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -313,6 +313,11 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp) mcc->parent_realize(dev, errp); } +static int hexagon_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return MMU_USER_IDX; +} + static void hexagon_cpu_init(Object *obj) { } @@ -341,6 +346,7 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data) &mcc->parent_phases); cc->class_by_name = hexagon_cpu_class_by_name; + cc->mmu_index = hexagon_cpu_mmu_index; cc->dump_state = hexagon_dump_state; cc->set_pc = hexagon_cpu_set_pc; cc->get_pc = hexagon_cpu_get_pc;
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/hexagon/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+)