diff mbox series

[RFC,PATCH-for-10.1,29/39] hw/arm: Build sbsa-ref.c once

Message ID	20250403235821.9909-30-philmd@linaro.org (mailing list archive)
State	New
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>, Pierrick Bouvier <pierrick.bouvier@linaro.org>, Richard Henderson <richard.henderson@linaro.org>, Markus Armbruster <armbru@redhat.com> Subject: [RFC PATCH-for-10.1 29/39] hw/arm: Build sbsa-ref.c once Date: Fri, 4 Apr 2025 01:58:11 +0200 Message-ID: <20250403235821.9909-30-philmd@linaro.org> In-Reply-To: <20250403235821.9909-1-philmd@linaro.org> References: <20250403235821.9909-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	single-binary: Make hw/arm/ common \| expand [RFC,PATCH-for-10.1,00/39] single-binary: Make hw/arm/ common [RFC,PATCH-for-10.1,01/39] target/arm: Implement per-binary TargetInfo structures [RFC,PATCH-for-10.1,02/39] target/arm: Register TYPE_BINARY_QEMU_SYSTEM_ARM/AARCH64 interfaces [RFC,PATCH-for-10.1,03/39] target/arm: Filter CPU types for binary [RFC,PATCH-for-10.1,04/39] hw/arm: Filter machine types for binary [RFC,PATCH-for-10.1,05/39] hw/arm/aspeed: Filter machine types for binary [RFC,PATCH-for-10.1,06/39] hw/arm/aspeed: Build objects once [RFC,PATCH-for-10.1,07/39] hw/arm/raspi: Filter machine types for binary [RFC,PATCH-for-10.1,08/39] hw/arm/raspi: Build objects once [RFC,PATCH-for-10.1,09/39] target/arm/cpregs: Include missing 'target/arm/cpu.h' header [RFC,PATCH-for-10.1,10/39] hw/arm/boot: Include missing 'system/memory.h' header [RFC,PATCH-for-10.1,11/39] hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h" [RFC,PATCH-for-10.1,12/39] target/arm/cpu-features: Include missing 'cpu.h' header [RFC,PATCH-for-10.1,13/39] target/arm/qmp: Include missing 'cpu.h' header [RFC,PATCH-for-10.1,14/39] target/arm/kvm: Include missing 'cpu-qom.h' header [RFC,PATCH-for-10.1,15/39] target/arm/hvf: Include missing 'cpu-qom.h' header [RFC,PATCH-for-10.1,16/39] hw/arm: Remove unnecessary 'cpu.h' header [RFC,PATCH-for-10.1,17/39] target/arm: Restrict inclusion of 'multiprocessing.h' [RFC,PATCH-for-10.1,18/39] target/arm: Move some definitions from 'cpu.h' to 'multiprocessing.h' [RFC,PATCH-for-10.1,19/39] hw/arm: Include missing 'target/arm/gtimer.h' header [RFC,PATCH-for-10.1,20/39] target/arm: Extract PSCI definitions to 'psci.h' [RFC,PATCH-for-10.1,21/39] target/arm: Extract feature definitions to 'cpu_has_feature.h' header [RFC,PATCH-for-10.1,22/39] target/arm: Add arm_cpu_has_feature() helper [RFC,PATCH-for-10.1,23/39] hw/arm/realview: Replace arm_feature() -> arm_cpu_has_feature() [RFC,PATCH-for-10.1,24/39] hw/arm/virt-acpi: Replace arm_feature() -> arm_cpu_has_feature() [RFC,PATCH-for-10.1,25/39] hw/arm: Build virt-acpi-build.c once [RFC,PATCH-for-10.1,26/39] system/hvf: Avoid including 'cpu.h' [RFC,PATCH-for-10.1,27/39] system/hvf: Expose hvf_enabled() to common code [RFC,PATCH-for-10.1,28/39] exec: Do not poison hardware accelerators [RFC,PATCH-for-10.1,29/39] hw/arm: Build sbsa-ref.c once [RFC,PATCH-for-10.1,30/39] target/arm: Replace target_ulong -> hwaddr in ARMMMUFaultInfo [RFC,PATCH-for-10.1,31/39] target/arm: Replace target_ulong -> uint64_t for HWBreakpoint [RFC,PATCH-for-10.1,32/39] target/arm: Replace target_ulong -> vaddr for CPUWatchpoint [RFC,PATCH-for-10.1,33/39] hw/core/machine: Allow dynamic registration of valid CPU types [RFC,PATCH-for-10.1,34/39] hw/arm/virt: Register valid CPU types dynamically [RFC,PATCH-for-10.1,35/39] hw/arm/virt: Replace TARGET_AARCH64 -> target_long_bits() [RFC,PATCH-for-10.1,36/39] target/arm: Expose Aarch64 helpers indistinctly [RFC,PATCH-for-10.1,37/39] hw/arm: Build virt.c once [RFC,PATCH-for-10.1,38/39] hw/arm: Move xen files to arm_common_ss[] [RFC,PATCH-for-10.1,39/39] hw/arm/meson: Remove arm_ss[] source set

Commit Message

Philippe Mathieu-Daudé April 3, 2025, 11:58 p.m. UTC

Since previous commit allowed the use of accelerator definitions
in common code, we can now move sbsa-ref.c to arm_common_ss[].

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 536e3c369c5..7eb49c7327f 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -14,7 +14,7 @@  arm_common_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32
 arm_common_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
 arm_common_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm8xx.c', 'npcm8xx_boards.c'))
 arm_common_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
-arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
+arm_common_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
 arm_common_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
 arm_common_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
 arm_common_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c'))