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Fri, 04 Apr 2025 08:28:04 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.170.227.223]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2297866e3ecsm33570655ad.198.2025.04.04.08.28.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Apr 2025 08:28:03 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH 2/2] hw/riscv/virt.c: change default CPU to 'max' Date: Fri, 4 Apr 2025 12:27:50 -0300 Message-ID: <20250404152750.332791-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250404152750.332791-1-dbarboza@ventanamicro.com> References: <20250404152750.332791-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In [1], minute 44, we have a hint from a Canonical kernel developer that the next Ubuntu LTS will be RVA23 compliant. If this really comes to pass, the 'virt' CPU won't run it by default - we'll need to either use 'rva23s64' or 'max' CPUs instead because rv64 is not RVA23 compliant. Other distros will follow suit eventually, given that RISC-V profiles provides the most stable ABI to build a distro in the RISC-V land. This exposes a long standing issue with the current rv64 CPU: it doesn't represent anything in particular. Extensions were added in it as time went by and we ended up with a CPU that has a random set of extensions. Changing the default 'virt' CPU to 'max' gives users a guarantee that the board will always run with the latest features/profile available in QEMU, which is the intention of most regular users. Using 'max' as default CPU is done by other QEMU archs like aarch64 so we'll be more compatible with everyone else. Note that this change does not affect existing scripts that are using the rv64 CPU, e.g. a command line like "-cpu rv64,v=true" will work the same after this patch. [1] https://fosdem.org/2025/schedule/event/fosdem-2025-6031-risc-v-hardware-where-are-we-/ Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c9d255d8a8..ff7a122bef 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1920,7 +1920,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) mc->desc = "RISC-V VirtIO board"; mc->init = virt_machine_init; mc->max_cpus = VIRT_CPUS_MAX; - mc->default_cpu_type = TYPE_RISCV_CPU_BASE; + mc->default_cpu_type = TYPE_RISCV_CPU_MAX; mc->block_default_type = IF_VIRTIO; mc->no_cdrom = 1; mc->pci_allow_0_address = true;