Message ID | 20250405140002.3537411-3-linux@roeck-us.net (mailing list archive) |
---|---|
State | New |
Headers | show
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Sat, 05 Apr 2025 07:00:08 -0700 (PDT) Received: from server.roeck-us.net ([2600:1700:e321:62f0:da43:aeff:fecc:bfd5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-229785bfea5sm50149875ad.54.2025.04.05.07.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Apr 2025 07:00:08 -0700 (PDT) From: Guenter Roeck <linux@roeck-us.net> To: qemu-devel@nongnu.org Cc: Richard Henderson <richard.henderson@linaro.org>, Peter Maydell <peter.maydell@linaro.org>, Bernhard Beschow <shentey@gmail.com>, Guenter Roeck <linux@roeck-us.net> Subject: [PATCH 2/2] hw/usb/hcd-dwc3: Set erstba-hi-lo property Date: Sat, 5 Apr 2025 07:00:02 -0700 Message-ID: <20250405140002.3537411-3-linux@roeck-us.net> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250405140002.3537411-1-linux@roeck-us.net> References: <20250405140002.3537411-1-linux@roeck-us.net> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=groeck7@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org |
Series |
Add property to support writing ERSTBA in high-low order
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expand
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diff --git a/hw/usb/hcd-dwc3.c b/hw/usb/hcd-dwc3.c index 0bceee2712..6783d55526 100644 --- a/hw/usb/hcd-dwc3.c +++ b/hw/usb/hcd-dwc3.c @@ -603,6 +603,7 @@ static void usb_dwc3_realize(DeviceState *dev, Error **errp) SysBusDevice *sbd = SYS_BUS_DEVICE(dev); Error *err = NULL; + qdev_prop_set_bit(DEVICE(&s->sysbus_xhci), "erstba-hi-lo", true); sysbus_realize(SYS_BUS_DEVICE(&s->sysbus_xhci), &err); if (err) { error_propagate(errp, err);
The dwc3 hardware requires the ERSTBA address to be written in high-low order. From information found in the Linux kernel: [Synopsys]- The host controller was design to support ERST setting during the RUN state. But since there is a limitation in controller in supporting separate ERSTBA_HI and ERSTBA_LO programming, It is supported when the ERSTBA is programmed in 64bit, or in 32 bit mode ERSTBA_HI before ERSTBA_LO [Synopsys]- The internal initialization of event ring fetches the "Event Ring Segment Table Entry" based on the indication of ERSTBA_LO written. Inform the XHCI core to expect ERSTBA to be written in high-low order. Signed-off-by: Guenter Roeck <linux@roeck-us.net> --- hw/usb/hcd-dwc3.c | 1 + 1 file changed, 1 insertion(+)