diff mbox series

target/mips: Fix MIPS16e translation

Message ID 20250412194003.181411-1-hauke@hauke-m.de (mailing list archive)
State New
Headers show
Series target/mips: Fix MIPS16e translation | expand

Commit Message

Hauke Mehrtens April 12, 2025, 7:40 p.m. UTC
Fix a wrong conversion to gen_op_addr_addi(). The framesize should be
added like it was done before.

This bug broke booting OpenWrt MIPS32 BE malta Linux system images
generated by OpenWrt.

Fixes: d0b24b7f50e1 ("target/mips: Use gen_op_addr_addi() when possible")
Cc: qemu-stable@nongnu.org
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 target/mips/tcg/mips16e_translate.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Philippe Mathieu-Daudé April 14, 2025, 10:23 a.m. UTC | #1
On 12/4/25 21:40, Hauke Mehrtens wrote:
> Fix a wrong conversion to gen_op_addr_addi(). The framesize should be
> added like it was done before.
> 
> This bug broke booting OpenWrt MIPS32 BE malta Linux system images
> generated by OpenWrt.
> 
> Fixes: d0b24b7f50e1 ("target/mips: Use gen_op_addr_addi() when possible")
> Cc: qemu-stable@nongnu.org
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> ---
>   target/mips/tcg/mips16e_translate.c.inc | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Oops...

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff mbox series

Patch

diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index a9af8f1e74..97da3456ea 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -306,7 +306,7 @@  static void gen_mips16_restore(DisasContext *ctx,
     int astatic;
     TCGv t0 = tcg_temp_new();
 
-    gen_op_addr_addi(ctx, t0, cpu_gpr[29], -framesize);
+    gen_op_addr_addi(ctx, t0, cpu_gpr[29], framesize);
 
     if (do_ra) {
         decr_and_load(ctx, 31, t0);
@@ -386,7 +386,7 @@  static void gen_mips16_restore(DisasContext *ctx,
         }
     }
 
-    gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], -framesize);
+    gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], framesize);
 }
 
 #if defined(TARGET_MIPS64)