diff mbox series

[v4,124/163] target/arm: Use tcg_gen_addcio_* for ADCS

Message ID 20250415192515.232910-125-richard.henderson@linaro.org (mailing list archive)
State New
Headers show
Series tcg: Convert to TCGOutOp structures | expand

Commit Message

Richard Henderson April 15, 2025, 7:24 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/tcg/translate-a64.c |  8 ++------
 target/arm/tcg/translate.c     | 17 +++--------------
 2 files changed, 5 insertions(+), 20 deletions(-)

Comments

Pierrick Bouvier April 16, 2025, 7 p.m. UTC | #1 
On 4/15/25 12:24, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/arm/tcg/translate-a64.c |  8 ++------
>   target/arm/tcg/translate.c     | 17 +++--------------
>   2 files changed, 5 insertions(+), 20 deletions(-)
> 
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
> index 934d66848a..99545a900d 100644
> --- a/target/arm/tcg/translate-a64.c
> +++ b/target/arm/tcg/translate-a64.c
> @@ -1076,11 +1076,9 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
>           TCGv_i64 cf_64 = tcg_temp_new_i64();
>           TCGv_i64 vf_64 = tcg_temp_new_i64();
>           TCGv_i64 tmp = tcg_temp_new_i64();
> -        TCGv_i64 zero = tcg_constant_i64(0);
>   
>           tcg_gen_extu_i32_i64(cf_64, cpu_CF);
> -        tcg_gen_add2_i64(result, cf_64, t0, zero, cf_64, zero);
> -        tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, zero);
> +        tcg_gen_addcio_i64(result, cf_64, t0, t1, cf_64);
>           tcg_gen_extrl_i64_i32(cpu_CF, cf_64);
>           gen_set_NZ64(result);
>   
> @@ -1094,12 +1092,10 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
>           TCGv_i32 t0_32 = tcg_temp_new_i32();
>           TCGv_i32 t1_32 = tcg_temp_new_i32();
>           TCGv_i32 tmp = tcg_temp_new_i32();
> -        TCGv_i32 zero = tcg_constant_i32(0);
>   
>           tcg_gen_extrl_i64_i32(t0_32, t0);
>           tcg_gen_extrl_i64_i32(t1_32, t1);
> -        tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, zero, cpu_CF, zero);
> -        tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, zero);
> +        tcg_gen_addcio_i32(cpu_NF, cpu_CF, t0_32, t1_32, cpu_CF);
>   
>           tcg_gen_mov_i32(cpu_ZF, cpu_NF);
>           tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
> index d280018138..e5aa76d44a 100644
> --- a/target/arm/tcg/translate.c
> +++ b/target/arm/tcg/translate.c
> @@ -493,20 +493,9 @@ static void gen_add_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
>   static void gen_adc_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
>   {
>       TCGv_i32 tmp = tcg_temp_new_i32();
> -    if (tcg_op_supported(INDEX_op_add2_i32, TCG_TYPE_I32, 0)) {
> -        tcg_gen_movi_i32(tmp, 0);
> -        tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, cpu_CF, tmp);
> -        tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1, tmp);
> -    } else {
> -        TCGv_i64 q0 = tcg_temp_new_i64();
> -        TCGv_i64 q1 = tcg_temp_new_i64();
> -        tcg_gen_extu_i32_i64(q0, t0);
> -        tcg_gen_extu_i32_i64(q1, t1);
> -        tcg_gen_add_i64(q0, q0, q1);
> -        tcg_gen_extu_i32_i64(q1, cpu_CF);
> -        tcg_gen_add_i64(q0, q0, q1);
> -        tcg_gen_extr_i64_i32(cpu_NF, cpu_CF, q0);
> -    }
> +
> +    tcg_gen_addcio_i32(cpu_NF, cpu_CF, t0, t1, cpu_CF);
> +
>       tcg_gen_mov_i32(cpu_ZF, cpu_NF);
>       tcg_gen_xor_i32(cpu_VF, cpu_NF, t0);
>       tcg_gen_xor_i32(tmp, t0, t1);

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff mbox series

Patch

diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 934d66848a..99545a900d 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -1076,11 +1076,9 @@  static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
         TCGv_i64 cf_64 = tcg_temp_new_i64();
         TCGv_i64 vf_64 = tcg_temp_new_i64();
         TCGv_i64 tmp = tcg_temp_new_i64();
-        TCGv_i64 zero = tcg_constant_i64(0);
 
         tcg_gen_extu_i32_i64(cf_64, cpu_CF);
-        tcg_gen_add2_i64(result, cf_64, t0, zero, cf_64, zero);
-        tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, zero);
+        tcg_gen_addcio_i64(result, cf_64, t0, t1, cf_64);
         tcg_gen_extrl_i64_i32(cpu_CF, cf_64);
         gen_set_NZ64(result);
 
@@ -1094,12 +1092,10 @@  static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
         TCGv_i32 t0_32 = tcg_temp_new_i32();
         TCGv_i32 t1_32 = tcg_temp_new_i32();
         TCGv_i32 tmp = tcg_temp_new_i32();
-        TCGv_i32 zero = tcg_constant_i32(0);
 
         tcg_gen_extrl_i64_i32(t0_32, t0);
         tcg_gen_extrl_i64_i32(t1_32, t1);
-        tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, zero, cpu_CF, zero);
-        tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, zero);
+        tcg_gen_addcio_i32(cpu_NF, cpu_CF, t0_32, t1_32, cpu_CF);
 
         tcg_gen_mov_i32(cpu_ZF, cpu_NF);
         tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index d280018138..e5aa76d44a 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -493,20 +493,9 @@  static void gen_add_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
 static void gen_adc_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
 {
     TCGv_i32 tmp = tcg_temp_new_i32();
-    if (tcg_op_supported(INDEX_op_add2_i32, TCG_TYPE_I32, 0)) {
-        tcg_gen_movi_i32(tmp, 0);
-        tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, cpu_CF, tmp);
-        tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1, tmp);
-    } else {
-        TCGv_i64 q0 = tcg_temp_new_i64();
-        TCGv_i64 q1 = tcg_temp_new_i64();
-        tcg_gen_extu_i32_i64(q0, t0);
-        tcg_gen_extu_i32_i64(q1, t1);
-        tcg_gen_add_i64(q0, q0, q1);
-        tcg_gen_extu_i32_i64(q1, cpu_CF);
-        tcg_gen_add_i64(q0, q0, q1);
-        tcg_gen_extr_i64_i32(cpu_NF, cpu_CF, q0);
-    }
+
+    tcg_gen_addcio_i32(cpu_NF, cpu_CF, t0, t1, cpu_CF);
+
     tcg_gen_mov_i32(cpu_ZF, cpu_NF);
     tcg_gen_xor_i32(cpu_VF, cpu_NF, t0);
     tcg_gen_xor_i32(tmp, t0, t1);