[v2,10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function

Commit Message

Alistair Francis Dec. 8, 2020, 10:56 p.m. UTC

Signed-off-by: Alistair Francis <[e-mail]>
Reviewed-by: Bin Meng <[e-mail]>
Tested-by: Bin Meng <[e-mail]>
---
 target/riscv/cpu.h | 2 ++
 target/riscv/cpu.c | 9 +++++++++
 2 files changed, 11 insertions(+)

Comments

Richard Henderson Dec. 9, 2020, 3:59 p.m. UTC | #1

On 12/8/20 4:56 PM, Alistair Francis wrote:
> +bool riscv_cpu_is_32bit(CPURISCVState *env)
> +{
> +    if (env->misa & RV64) {
> +        return false;
> +    }
> +
> +    return true;

Is this ever going to more than

    return !(env->misa & RV64);

?


r~

Alistair Francis Dec. 9, 2020, 10:26 p.m. UTC | #2

On Wed, Dec 9, 2020 at 7:59 AM Richard Henderson
<[e-mail]> wrote:
>
> On 12/8/20 4:56 PM, Alistair Francis wrote:
> > +bool riscv_cpu_is_32bit(CPURISCVState *env)
> > +{
> > +    if (env->misa & RV64) {
> > +        return false;
> > +    }
> > +
> > +    return true;
>
> Is this ever going to more than
>
>     return !(env->misa & RV64);

Eventually this could also depend on mstatus, to allow a 32-bit kernel
to run on a 64-bit firmware.

It will also hopefully one day be configurable by hypervisors.

Alistair

>
> ?
>
>
> r~

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9c064f3094..6339e84819 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -384,6 +384,8 @@  FIELD(TB_FLAGS, VILL, 8, 1)
 /* Is a Hypervisor instruction load/store allowed? */
 FIELD(TB_FLAGS, HLSX, 9, 1)
 
+bool riscv_cpu_is_32bit(CPURISCVState *env);
+
 /*
  * A simplification for VLMAX
  * = (1 << LMUL) * VLEN / (8 * (1 << SEW))
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6a0264fc6b..32a6916b8a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -108,6 +108,15 @@  const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
     }
 }
 
+bool riscv_cpu_is_32bit(CPURISCVState *env)
+{
+    if (env->misa & RV64) {
+        return false;
+    }
+
+    return true;
+}
+
 static void set_misa(CPURISCVState *env, target_ulong misa)
 {
     env->misa_mask = env->misa = misa;