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[71.37.54.227]) by smtp.googlemail.com with ESMTPSA id l93sm2963966qgf.42.2016.06.16.12.04.06 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 16 Jun 2016 12:04:06 -0700 (PDT) To: David Gibson , Anton Blanchard References: <1464318298-2456-1-git-send-email-david@gibson.dropbear.id.au> <1464318298-2456-4-git-send-email-david@gibson.dropbear.id.au> <20160615221719.12f246dd@kryten> <20160616051928.GA1642@voom.fritz.box> From: Richard Henderson Message-ID: <2fe8f40e-27ba-23b7-5d11-f75eda95568d@twiddle.net> Date: Thu, 16 Jun 2016 12:04:04 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 MIME-Version: 1.0 In-Reply-To: <20160616051928.GA1642@voom.fritz.box> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400d:c09::241 Subject: Re: [Qemu-devel] [PULL 03/13] target-ppc: Use 32-bit rotate instead of deposit + 64-bit rotate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-ppc@nongnu.org, agraf@suse.de, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP On 06/15/2016 10:19 PM, David Gibson wrote: > On Wed, Jun 15, 2016 at 10:17:19PM +1000, Anton Blanchard wrote: >> Hi, >> >>> From: Richard Henderson >>> >>> A 32-bit rotate insn is more common on hosts than a deposit insn, >>> and if the host has neither the result is truely horrific. >>> >>> At the same time, tidy up the temporaries within these functions, >>> drop the over-use of "likely", drop some checks for identity that >>> will also be checked by tcg-op.c functions, and special case mask >>> without rotate within rlwinm. >> >> This breaks masks that wrap: >> >> li r3,-1 >> li r4,-1 >> rlwnm r3,r3,r4,22,8 >> >> We expect: >> >> ffffffffff8003ff >> >> But get: >> >> ff8003ff >> >> Anton > > Bother. I've tentatively put a revert into ppc-for-2.7. Richard, do > you have a better idea how to fix it? Please try the following. r~ Tested-by: Anton Blanchard >From f6059bc0e1303d898be2132a444bd58478a0eba0 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 16 Jun 2016 19:00:12 +0000 Subject: [PATCH] target-ppc: Fix rlwimi, rlwinm, rlwnm In 63ae0915f8ec, I arranged to use a 32-bit rotate, without considering the effect of a mask value that wraps around to the high bits of the word. Signed-off-by: Richard Henderson --- target-ppc/translate.c | 73 +++++++++++++++++++++++++++++++++++--------------- 1 file changed, 52 insertions(+), 21 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index b689475..12cfa37 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1636,7 +1636,6 @@ static void gen_rlwimi(DisasContext *ctx) tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); } else { target_ulong mask; - TCGv_i32 t0; TCGv t1; #if defined(TARGET_PPC64) @@ -1645,12 +1644,21 @@ static void gen_rlwimi(DisasContext *ctx) #endif mask = MASK(mb, me); - t0 = tcg_temp_new_i32(); t1 = tcg_temp_new(); - tcg_gen_trunc_tl_i32(t0, t_rs); - tcg_gen_rotli_i32(t0, t0, sh); - tcg_gen_extu_i32_tl(t1, t0); - tcg_temp_free_i32(t0); + if (mask <= 0xffffffffu) { + TCGv_i32 t0 = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t0, t_rs); + tcg_gen_rotli_i32(t0, t0, sh); + tcg_gen_extu_i32_tl(t1, t0); + tcg_temp_free_i32(t0); + } else { +#if defined(TARGET_PPC64) + tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); + tcg_gen_rotli_i64(t1, t1, sh); +#else + g_assert_not_reached(); +#endif + } tcg_gen_andi_tl(t1, t1, mask); tcg_gen_andi_tl(t_ra, t_ra, ~mask); @@ -1678,20 +1686,30 @@ static void gen_rlwinm(DisasContext *ctx) tcg_gen_ext32u_tl(t_ra, t_rs); tcg_gen_shri_tl(t_ra, t_ra, mb); } else { + target_ulong mask; #if defined(TARGET_PPC64) mb += 32; me += 32; #endif + mask = MASK(mb, me); + if (sh == 0) { - tcg_gen_andi_tl(t_ra, t_rs, MASK(mb, me)); - } else { + tcg_gen_andi_tl(t_ra, t_rs, mask); + } else if (mask <= 0xffffffffu) { TCGv_i32 t0 = tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t0, t_rs); tcg_gen_rotli_i32(t0, t0, sh); - tcg_gen_andi_i32(t0, t0, MASK(mb, me)); + tcg_gen_andi_i32(t0, t0, mask); tcg_gen_extu_i32_tl(t_ra, t0); tcg_temp_free_i32(t0); + } else { +#if defined(TARGET_PPC64) + tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); + tcg_gen_rotli_i64(t_ra, t_ra, sh); + tcg_gen_andi_i64(t_ra, t_ra, mask); +#else + g_assert_not_reached(); +#endif } } if (unlikely(Rc(ctx->opcode) != 0)) { @@ -1707,24 +1725,37 @@ static void gen_rlwnm(DisasContext *ctx) TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; uint32_t mb = MB(ctx->opcode); uint32_t me = ME(ctx->opcode); - TCGv_i32 t0, t1; + target_ulong mask; #if defined(TARGET_PPC64) mb += 32; me += 32; #endif + mask = MASK(mb, me); - t0 = tcg_temp_new_i32(); - t1 = tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t0, t_rb); - tcg_gen_trunc_tl_i32(t1, t_rs); - tcg_gen_andi_i32(t0, t0, 0x1f); - tcg_gen_rotl_i32(t1, t1, t0); - tcg_temp_free_i32(t0); + if (mask <= 0xffffffffu) { + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t0, t_rb); + tcg_gen_trunc_tl_i32(t1, t_rs); + tcg_gen_andi_i32(t0, t0, 0x1f); + tcg_gen_rotl_i32(t1, t1, t0); + tcg_gen_extu_i32_tl(t_ra, t1); + tcg_temp_free_i32(t0); + tcg_temp_free_i32(t1); + } else { +#if defined(TARGET_PPC64) + TCGv_i64 t0 = tcg_temp_new_i64(); + tcg_gen_andi_i64(t0, t_rb, 0x1f); + tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); + tcg_gen_rotl_i64(t_ra, t_ra, t0); + tcg_temp_free_i64(t0); +#else + g_assert_not_reached(); +#endif + } - tcg_gen_andi_i32(t1, t1, MASK(mb, me)); - tcg_gen_extu_i32_tl(t_ra, t1); - tcg_temp_free_i32(t1); + tcg_gen_andi_tl(t_ra, t_ra, mask); if (unlikely(Rc(ctx->opcode) != 0)) { gen_set_Rc0(ctx, t_ra); -- 2.5.5