diff mbox series

[v1,3/5] target/riscv: Fix 32-bit HS mode access permissions

Message ID 36b83d45e6cdc072574363b6ea937b0a5dad245a.1616002766.git.alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show
Series RISC-V: Convert the CSR access functions to use | expand

Commit Message

Alistair Francis March 17, 2021, 5:39 p.m. UTC 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index da9baff6fb..d10f47c3fb 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -181,7 +181,11 @@  static RiscVException hmode(CPURISCVState *env, int csrno)
 static RiscVException hmode32(CPURISCVState *env, int csrno)
 {
     if (!riscv_cpu_is_32bit(env)) {
-        return RISCV_EXCP_NONE;
+        if (riscv_cpu_virt_enabled(env)) {
+            return RISCV_EXCP_ILLEGAL_INST;
+        } else {
+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+        }
     }
 
     return hmode(env, csrno);