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14 Dec 2020 12:17:43 -0800 IronPort-SDR: JsXFMv4M+7Es7jWNDt6Ne2GiJ9XR8yT05itif7CojIPQER9XGijzyKU+23d7/hCVrvWXpYgNgh amBCAUCYaKoXi4/55ryArE2CRzrgCzBpgYQFCe5q0gw0SNEIgqIfXu7gVJCqbRrEKSWWHEZu97 zygbE4F8WyR504wdCP7Npz6jPhVs72uUkJ0CJKPLpZI5bnCrgsUlJfuPUrfOJraRnQlRBrZPME WPnhUMdBrppWP+8aUnZJqRJYaGm/ut5EtxVHxO+Q3wJYmBQ/rKQuM4IqozCHOcdivJlbe08NTF +UA= WDCIronportException: Internal Received: from cnf006900.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.62.52]) by uls-op-cesaip02.wdc.com with ESMTP; 14 Dec 2020 12:33:59 -0800 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs Date: Mon, 14 Dec 2020 12:33:58 -0800 Message-Id: <3b6338af937d0d3aa0858ba1a4ad0fd9e759be66.1607967113.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=61015ee87=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Currently the riscv_is_32_bit() function only supports the generic rv32 CPUs. Extend the function to support the SiFive and LowRISC CPUs as well. Signed-off-by: Alistair Francis --- hw/riscv/boot.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index d62f3dc758..3c70ac75d7 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -41,7 +41,17 @@ bool riscv_is_32_bit(MachineState *machine) { - if (!strncmp(machine->cpu_type, "rv32", 4)) { + /* + * To determine if the CPU is 32-bit we need to check a few different CPUs. + * + * If the CPU starts with rv32 + * If the CPU is a sifive 3 seriries CPU (E31, U34) + * If it's the Ibex CPU + */ + if (!strncmp(machine->cpu_type, "rv32", 4) || + (!strncmp(machine->cpu_type, "sifive", 6) && + machine->cpu_type[8] == '3') || + !strncmp(machine->cpu_type, "lowrisc-ibex", 12)) { return true; } else { return false;