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13 Apr 2021 16:12:54 -0700 IronPort-SDR: qTfIjjiwEATE/eNmoDYNxEkDjqQaFKuaqyI1yepECemBtwS27MayXmXJHlANj9p/QYOVinhVBY DKfS8D37xzhCzZQqjGqxO5TNEq1A9nmulDGmBYMvRf/yMkJY9Zd7OkE/l1I2Niuvx0r7Tj4gXQ xtnyg1VZS4j/AeHGRCDF11c9E3w7ktcf589BPLYDOnKP1MMaAKqpDpzVn9IB3TIPNwQE1t/u8O lOvbZ1S1+KMjuyemCQUcN4qykkniNDthH1hJSIYsTPuFh5r5IbYeZmAxaqveUfpWy4wt28zOaK Clg= WDCIronportException: Internal Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.17]) by uls-op-cesaip02.wdc.com with ESMTP; 13 Apr 2021 16:33:23 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 1/9] target/riscv: Remove the hardcoded RVXLEN macro Date: Wed, 14 Apr 2021 09:33:16 +1000 Message-Id: <3eea7ff02e990d9d9cb906be9eb821eaf1ee5408.1618356725.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=730c0c5bd=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng --- target/riscv/cpu.h | 6 ------ target/riscv/cpu.c | 6 +++++- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0a33d387ba..ef838f5fbf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -53,12 +53,6 @@ #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) -#if defined(TARGET_RISCV32) -#define RVXLEN RV32 -#elif defined(TARGET_RISCV64) -#define RVXLEN RV64 -#endif - #define RV(x) ((target_ulong)1 << (x - 'A')) #define RVI RV('I') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d6ed80f6b..92c3195531 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -147,7 +147,11 @@ static void set_resetvec(CPURISCVState *env, int resetvec) static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#if defined(TARGET_RISCV32) + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#elif defined(TARGET_RISCV64) + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#endif set_priv_version(env, PRIV_VERSION_1_11_0); }