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[v1,02/15] target/riscv: Report errors validating 2nd-stage PTEs

Message ID 416aa978887e9f86307616189207a5b015f8e82e.1587917657.git.alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show
Series RISC-V: Update the Hypervisor spec to v0.6 | expand

Commit Message

Alistair Francis April 26, 2020, 4:19 p.m. UTC 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)
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Patch

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ed64190386..0d4a7b752d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -456,8 +456,13 @@  restart:
             hwaddr vbase;
 
             /* Do the second stage translation on the base PTE address. */
-            get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_LOAD,
-                                 mmu_idx, false, true);
+            int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
+                                                 base, MMU_DATA_LOAD,
+                                                 mmu_idx, false, true);
+
+            if (vbase_ret != TRANSLATE_SUCCESS) {
+                return vbase_ret;
+            }
 
             pte_addr = vbase + idx * ptesize;
         } else {