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Thu, 01 Apr 2021 03:41:15 -0700 (PDT) Received: from localhost.localdomain ([147.75.106.138]) by smtp.gmail.com with ESMTPSA id a6sm1069066otq.79.2021.04.01.03.41.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 03:41:15 -0700 (PDT) From: Haibo Xu To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [PATCH v2 4/6] hw/intc/arm_gicv3: Enable support for setting vGIC maintenance IRQ Date: Thu, 1 Apr 2021 10:40:56 +0000 Message-Id: <49a4944e2f148c56938380b981afe154b7a8b7ee.1617272690.git.haibo.xu@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=haibo.xu@linaro.org; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, richard.henderson@linaro.org, abologna@redhat.com, Haibo Xu , philmd@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Using the new VGIC KVM device attribute to set the maintenance IRQ. This is fixed to use IRQ 25(PPI 9), as a platform decision matching the arm64 SBSA recommendation. Signed-off-by: Haibo Xu --- hw/arm/virt.c | 5 +++++ hw/intc/arm_gicv3_common.c | 1 + hw/intc/arm_gicv3_kvm.c | 16 ++++++++++++++++ include/hw/intc/arm_gicv3_common.h | 1 + 4 files changed, 23 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index aa2bbd14e0..92d46ebcfe 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -663,6 +663,11 @@ static void create_gic(VirtMachineState *vms) qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); } + + if (kvm_irqchip_in_kernel()) { + bool el2 = object_property_get_bool(OBJECT(first_cpu), "el2", NULL); + qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", el2); + } } else { if (!kvm_irqchip_in_kernel()) { qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 58ef65f589..3ac10c8e61 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -495,6 +495,7 @@ static Property arm_gicv3_common_properties[] = { DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32), DEFINE_PROP_UINT32("revision", GICv3State, revision, 3), DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0), + DEFINE_PROP_BOOL("has-virtualization-extensions", GICv3State, virt_extn, 0), DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions, redist_region_count, qdev_prop_uint32, uint32_t), DEFINE_PROP_END_OF_LIST(), diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 65a4c880a3..1e1ca66e2c 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -826,6 +826,22 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); + if (s->virt_extn) { + bool maint_irq_allowed; + uint32_t maint_irq = 25; + + maint_irq_allowed = + kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ, 0); + if (!maint_irq_allowed) { + error_setg(errp, "VGICv3 setting maintenance IRQ are not " + "supported by this host kernel"); + return; + } + + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ, + 0, &maint_irq, true, &error_abort); + } + kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0); diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index 91491a2f66..921ddc2c5f 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -220,6 +220,7 @@ struct GICv3State { uint32_t num_irq; uint32_t revision; bool security_extn; + bool virt_extn; bool irq_reset_nonsecure; bool gicd_no_migration_shift_bug;