diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/idef-parser/parser-helpers.c
index 4af020933a..0f1713ae4c 100644
--- a/target/hexagon/idef-parser/parser-helpers.c
+++ b/target/hexagon/idef-parser/parser-helpers.c
@@ -1,34 +1,35 @@
 /*
  *  Copyright(c) 2019-2023 rev.ng Labs Srl. All Rights Reserved.
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *  the Free Software Foundation; either version 2 of the License, or
  *  (at your option) any later version.
  *
  *  This program is distributed in the hope that it will be useful,
  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *  GNU General Public License for more details.
  *
  *  You should have received a copy of the GNU General Public License
  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <assert.h>
 #include <inttypes.h>
 #include <stdarg.h>
 #include <stdbool.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
 #include <unistd.h>
 
 #include "idef-parser.h"
 #include "parser-helpers.h"
 #include "idef-parser.tab.h"
 #include "idef-parser.yy.h"
+#include "qemu/compiler.h"
 
 void yyerror(YYLTYPE *locp,
              yyscan_t scanner __attribute__((unused)),
@@ -621,51 +622,51 @@ static void gen_sub_op(Context *c, YYLTYPE *locp, unsigned bit_width,
 static void gen_asl_op(Context *c, YYLTYPE *locp, unsigned bit_width,
                        bool op_is64bit, const char *bit_suffix,
                        HexValue *res, enum OpTypes op_types,
                        HexValue *op1, HexValue *op2)
 {
     HexValue op1_m = *op1;
     HexValue op2_m = *op2;
     switch (op_types) {
     case IMM_IMM: {
         HexSignedness signedness = bin_op_signedness(c, locp,
                                                      op1->signedness,
                                                      op2->signedness);
         gen_c_int_type(c, locp, bit_width, signedness);
         OUT(c, locp, " ", res,
             " = ", op1, " << ", op2, ";\n");
     } break;
     case REG_IMM: {
         OUT(c, locp, "if (", op2, " >= ", &bit_width, ") {\n");
         OUT(c, locp, "tcg_gen_movi_", bit_suffix, "(", res, ", 0);\n");
         OUT(c, locp, "} else {\n");
         OUT(c, locp, "tcg_gen_shli_", bit_suffix,
                 "(", res, ", ", op1, ", ", op2, ");\n");
         OUT(c, locp, "}\n");
     } break;
     case IMM_REG:
         op1_m.bit_width = bit_width;
         op1_m = rvalue_materialize(c, locp, &op1_m);
-        /* fallthrough */
+        fallthrough;
     case REG_REG: {
         OUT(c, locp, "tcg_gen_shl_", bit_suffix,
             "(", res, ", ", &op1_m, ", ", op2, ");\n");
     } break;
     }
     if (op_types == IMM_REG || op_types == REG_REG) {
         /*
          * Handle left shift by 64/32 which hexagon-sim expects to clear out
          * register
          */
         HexValue zero = gen_constant(c, locp, "0", bit_width, UNSIGNED);
         HexValue edge = gen_imm_value(c, locp, bit_width, bit_width, UNSIGNED);
         edge = rvalue_materialize(c, locp, &edge);
         if (op_is64bit) {
             op2_m = gen_rvalue_extend(c, locp, &op2_m);
         }
         op1_m = rvalue_materialize(c, locp, &op1_m);
         op2_m = rvalue_materialize(c, locp, &op2_m);
         OUT(c, locp, "tcg_gen_movcond_i", &bit_width);
         OUT(c, locp, "(TCG_COND_GEU, ", res, ", ", &op2_m, ", ", &edge);
         OUT(c, locp, ", ", &zero, ", ", res, ");\n");
     }
 }
@@ -800,41 +801,41 @@ static void gen_andl_op(Context *c, YYLTYPE *locp, unsigned bit_width,
 static void gen_minmax_op(Context *c, YYLTYPE *locp, unsigned bit_width,
                           HexValue *res, enum OpTypes op_types,
                           HexValue *op1, HexValue *op2, bool minmax)
 {
     const char *mm;
     HexValue op1_m = *op1;
     HexValue op2_m = *op2;
     bool is_unsigned;
 
     assert_signedness(c, locp, res->signedness);
     is_unsigned = res->signedness == UNSIGNED;
 
     if (minmax) {
         /* Max */
         mm = is_unsigned ? "tcg_gen_umax" : "tcg_gen_smax";
     } else {
         /* Min */
         mm = is_unsigned ? "tcg_gen_umin" : "tcg_gen_smin";
     }
     switch (op_types) {
     case IMM_IMM:
         yyassert(c, locp, false, "MINMAX between IMM op IMM, not handled!");
         break;
     case IMM_REG:
         op1_m.bit_width = bit_width;
         op1_m = rvalue_materialize(c, locp, &op1_m);
         OUT(c, locp, mm, "_i", &bit_width, "(");
         OUT(c, locp, res, ", ", &op1_m, ", ", op2, ");\n");
         break;
     case REG_IMM:
         op2_m.bit_width = bit_width;
         op2_m = rvalue_materialize(c, locp, &op2_m);
-        /* Fallthrough */
+        fallthrough;
     case REG_REG:
         OUT(c, locp, mm, "_i", &bit_width, "(");
         OUT(c, locp, res, ", ", op1, ", ", &op2_m, ");\n");
         break;
     }
 }
 
 /* Code generation functions */
