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X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [PATCH v1 3/4] target/riscv: Implement the stval illegal instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The stval register can optionally contain the faulting instruction on an illegal instruction exception. This patch adds support for setting the stval register based on the CPU feature. Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 ++- target/riscv/helper.c | 13 +++++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1bc46aa952..b797850816 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -86,7 +86,8 @@ so a cpu features bitfield is required */ enum { RISCV_FEATURE_MMU, - RISCV_FEATURE_MTVAL_INST + RISCV_FEATURE_MTVAL_INST, + RISCV_FEATURE_STVAL_INST }; #define USER_VERSION_2_02_0 0x00020200 diff --git a/target/riscv/helper.c b/target/riscv/helper.c index bd78bcff28..924a49d06f 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -466,9 +466,18 @@ void riscv_cpu_do_interrupt(CPUState *cs) ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr); } env->stval = env->badaddr; + } else if (cs->exception_index & RISCV_EXCP_ILLEGAL_INST) { + if (riscv_feature(env, RISCV_FEATURE_STVAL_INST)) { + /* The stval register can optionally also be used to + * return the faulting instruction bits on an illegal + * instruction exception. + */ + env->stval = env->bins; + } else { + env->stval = 0; + } } else { - /* otherwise we must clear sbadaddr/stval - * todo: support populating stval on illegal instructions */ + /* Otherwise we must clear mbadaddr/stval */ env->stval = 0; }