From patchwork Mon Mar 11 07:09:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dmitriy Sharikhin X-Patchwork-Id: 13588325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0C23C54E58 for ; Mon, 11 Mar 2024 07:10:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rjZnZ-0000WC-BA; Mon, 11 Mar 2024 03:10:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rjZnX-0000W0-H9 for qemu-devel@nongnu.org; Mon, 11 Mar 2024 03:10:11 -0400 Received: from mta-04.yadro.com ([89.207.88.248]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rjZnS-0007ao-II for qemu-devel@nongnu.org; Mon, 11 Mar 2024 03:10:11 -0400 DKIM-Filter: OpenDKIM Filter v2.11.0 mta-04.yadro.com BD0BCC0002 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yadro.com; s=mta-04; t=1710140995; bh=VHLIoeIBKixZfRq69lC5AyT/CxiPVrcG8b6PD0NnrWM=; h=From:To:Subject:Date:Message-ID:Content-Type:MIME-Version:From; b=Ie5PpJ6YaUnT9wrgQA85mcBCH4VWp0kd409cBq/y2Zx0vCNdZQrQnod3yCrXdz7yk Ma4B7Ob/OuiSulb2HHW46IEU1QGvoTKuWfurYv3MQSZ90w+ZeItYPlQ9GqlxOj4nXD Tr7r8Y0aH/GH8X0M96O3Nh8zTuPbDZZnlc2XBkrgpPIiDT1F9blVMOAqeaVWpnXkrO 79U8EB5jrRsNQzbiFNfA2+U+jVxGzVb2rK8b7APuLLJUbqo0yIZv8xURY9BPrikUmb OBMgLsA/nAM5S4d66o6jB68T8XWr6fcnUHm+t+yiZVEIavq07w6Y74KPCY6YXFO6j5 Onxm23pR8vaAw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yadro.com; s=mta-03; t=1710140995; bh=VHLIoeIBKixZfRq69lC5AyT/CxiPVrcG8b6PD0NnrWM=; h=From:To:Subject:Date:Message-ID:Content-Type:MIME-Version:From; b=hFVpaFBN7tueofD9V82M+fVtUrM6upDreIhBXcYRA3r4wkzucv154X1hGDgQg2P9Z 1xchEwaF9eC6ZTXLJ9xerUvUfCEmLDq7zd3DSllbaKBWS6X/5pznKygts+uBVhaB3W 3/T1dfrm5PzXnLmZK6t0h8qr4BemKr6tYIGgJQ1kM9CSfOzeAsdwVQxr18wk2X7UAO 9xMWpTo7aXxlJ9Rg9Wp86GD9UHebTbmOvaE/IWLAf4Z0U+x79LGf2Gv4nyHO/wq+Fs wxKdXouUCJ4r0GSUSdfowkK0O4GOSDI/ND5ybpnQvDhRWNVtQUa0jWRz5i8jiTQ5Dx MVUHzRJPEOPpw== From: Dmitriy Sharikhin To: "qemu-devel@nongnu.org" CC: Igor Kononenko , "Alexander A. Filippov" , Alexander Amelkin , "philmd@linaro.org" Subject: [PATCH v2] hw: gpio: introduce pcf8574 driver Thread-Topic: [PATCH v2] hw: gpio: introduce pcf8574 driver Thread-Index: AQHac4MejGvP5o2kLE24WSmT4U5j9w== Date: Mon, 11 Mar 2024 07:09:54 +0000 Message-ID: <56678f4f0c1e526b7b5a04104171e4feb372e7c2.camel@yadro.com> References: <0cbde20b-db66-4894-b498-8360b8006693@linaro.org> In-Reply-To: <0cbde20b-db66-4894-b498-8360b8006693@linaro.org> Accept-Language: ru-RU, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Content-ID: MIME-Version: 1.0 Received-SPF: pass client-ip=89.207.88.248; envelope-from=d.sharikhin@yadro.com; helo=mta-04.yadro.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org NXP PCF8574 and compatible ICs are simple I2C GPIO expanders. PCF8574 incorporates quasi-bidirectional IO, and simple communication protocol, when IO read is I2C byte read, and IO write is I2C byte write. User can think of it as open-drain port, when line high state is input and line low state is output. Signed-off-by: Dmitrii Sharikhin Reviewed-by: Philippe Mathieu-Daudé --- MAINTAINERS | 6 ++ hw/gpio/Kconfig | 4 + hw/gpio/meson.build | 1 + hw/gpio/pcf8574.c | 162 ++++++++++++++++++++++++++++++++++++++ include/hw/gpio/pcf8574.h | 15 ++++ 5 files changed, 188 insertions(+) create mode 100644 hw/gpio/pcf8574.c create mode 100644 include/hw/gpio/pcf8574.h diff --git a/MAINTAINERS b/MAINTAINERS index 65dfdc9677..bb1981d02e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2499,6 +2499,12 @@ S: Maintained F: hw/i2c/i2c_mux_pca954x.c F: include/hw/i2c/i2c_mux_pca954x.h +pcf8574 +M: Dmitrii Sharikhin +S: Maintained +F: hw/gpio/pcf8574.c +F: include/gpio/pcf8574.h + Generic Loader M: Alistair Francis S: Maintained diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index d2cf3accc8..bb731ff4ce 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -16,3 +16,7 @@ config GPIO_PWR config SIFIVE_GPIO bool + +config PCF8574 + bool + depends on I2C diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 8a8d03d885..c0d9a3c757 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -15,3 +15,4 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files( )) system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c')) system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c')) +system_ss.add(when: 'CONFIG_PCF8574', if_true: files('pcf8574.c')) diff --git a/hw/gpio/pcf8574.c b/hw/gpio/pcf8574.c new file mode 100644 index 0000000000..d37909e2ad --- /dev/null +++ b/hw/gpio/pcf8574.c @@ -0,0 +1,162 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * NXP PCF8574 8-port I2C GPIO expansion chip. + * Copyright (c) 2024 KNS Group (YADRO). + * Written by Dmitrii Sharikhin + */ + +#include "qemu/osdep.h" +#include "hw/i2c/i2c.h" +#include "hw/gpio/pcf8574.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qom/object.h" + +/* + * PCF8574 and compatible chips incorporate quasi-bidirectional + * IO. Electrically it means that device sustain pull-up to line + * unless IO port is configured as output _and_ driven low. + * + * IO access is implemented as simple I2C single-byte read + * or write operation. So, to configure line to input user write 1 + * to corresponding bit. To configure line to output and drive it low + * user write 0 to corresponding bit. + * + * In essence, user can think of quasi-bidirectional IO as + * open-drain line, except presence of builtin rising edge acceleration + * embedded in PCF8574 IC + * + * PCF8574 has interrupt request line, which is being pulled down when + * port line state differs from last read. Port read operation clears + * state and INT line returns to high state via pullup. + */ + +OBJECT_DECLARE_SIMPLE_TYPE(PCF8574State, PCF8574) + +#define PORTS_COUNT (8) + +struct PCF8574State { + I2CSlave parent_obj; + uint8_t lastrq; /* Last requested state. If changed - assert irq */ + uint8_t input; /* external electrical line state */ + uint8_t output; /* Pull-up (1) or drive low (0) on bit */ + qemu_irq handler[PORTS_COUNT]; + qemu_irq intrq; /* External irq request */ +}; + +static void pcf8574_reset(DeviceState *dev) +{ + PCF8574State *s = PCF8574(dev); + s->lastrq = MAKE_64BIT_MASK(0, PORTS_COUNT); + s->input = MAKE_64BIT_MASK(0, PORTS_COUNT); + s->output = MAKE_64BIT_MASK(0, PORTS_COUNT); +} + +static inline uint8_t pcf8574_line_state(PCF8574State *s) +{ + /* we driving line low or external circuit does that */ + return s->input & s->output; +} + +static uint8_t pcf8574_rx(I2CSlave *i2c) +{ + PCF8574State *s = PCF8574(i2c); + uint8_t linestate = pcf8574_line_state(s); + if (s->lastrq != linestate) { + s->lastrq = linestate; + if (s->intrq) { + qemu_set_irq(s->intrq, 1); + } + } + return linestate; +} + +static int pcf8574_tx(I2CSlave *i2c, uint8_t data) +{ + PCF8574State *s = PCF8574(i2c); + uint8_t prev; + uint8_t diff; + uint8_t actual; + int line = 0; + + prev = pcf8574_line_state(s); + s->output = data; + actual = pcf8574_line_state(s); + + for (diff = (actual ^ prev); diff; diff &= ~(1 << line)) { + line = ctz32(diff); + if (s->handler[line]) { + qemu_set_irq(s->handler[line], (actual >> line) & 1); + } + } + + if (s->intrq) { + qemu_set_irq(s->intrq, actual == s->lastrq); + } + + return 0; +} + +static const VMStateDescription vmstate_pcf8574 = { + .name = "pcf8574", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_I2C_SLAVE(parent_obj, PCF8574State), + VMSTATE_UINT8(lastrq, PCF8574State), + VMSTATE_UINT8(input, PCF8574State), + VMSTATE_UINT8(output, PCF8574State), + VMSTATE_END_OF_LIST() + } +}; + +static void pcf8574_gpio_set(void *opaque, int line, int level) +{ + PCF8574State *s = (PCF8574State *) opaque; + assert(line >= 0 && line < ARRAY_SIZE(s->handler)); + + if (level) { + s->input |= (1 << line); + } else { + s->input &= ~(1 << line); + } + + if (pcf8574_line_state(s) != s->lastrq && s->intrq) { + qemu_set_irq(s->intrq, 0); + } +} + +static void pcf8574_realize(DeviceState *dev, Error **errp) +{ + PCF8574State *s = PCF8574(dev); + + qdev_init_gpio_in(dev, pcf8574_gpio_set, ARRAY_SIZE(s->handler)); + qdev_init_gpio_out(dev, s->handler, ARRAY_SIZE(s->handler)); + qdev_init_gpio_out_named(dev, &s->intrq, "nINT", 1); +} + +static void pcf8574_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); + + k->recv = pcf8574_rx; + k->send = pcf8574_tx; + dc->realize = pcf8574_realize; + dc->reset = pcf8574_reset; + dc->vmsd = &vmstate_pcf8574; +} + +static const TypeInfo pcf8574_infos[] = { + { + .name = TYPE_PCF8574, + .parent = TYPE_I2C_SLAVE, + .instance_size = sizeof(PCF8574State), + .class_init = pcf8574_class_init, + } +}; + +DEFINE_TYPES(pcf8574_infos); diff --git a/include/hw/gpio/pcf8574.h b/include/hw/gpio/pcf8574.h new file mode 100644 index 0000000000..3291d7dbbc --- /dev/null +++ b/include/hw/gpio/pcf8574.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * NXP PCF8574 8-port I2C GPIO expansion chip. + * + * Copyright (c) 2024 KNS Group (YADRO). + * Written by Dmitrii Sharikhin + */ + +#ifndef _HW_GPIO_PCF8574 +#define _HW_GPIO_PCF8574 + +#define TYPE_PCF8574 "pcf8574" + +#endif /* _HW_GPIO_PCF8574 */