From patchwork Mon May 9 11:58:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 9045591 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8A5D39F30C for ; Mon, 9 May 2016 11:59:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E0F6E2011E for ; Mon, 9 May 2016 11:59:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2EF0720115 for ; Mon, 9 May 2016 11:59:07 +0000 (UTC) Received: from localhost ([::1]:40770 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1azjq6-0007YZ-9z for patchwork-qemu-devel@patchwork.kernel.org; Mon, 09 May 2016 07:59:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1azjpz-0007Vi-0i for qemu-devel@nongnu.org; Mon, 09 May 2016 07:59:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1azjpu-0002Cv-MH for qemu-devel@nongnu.org; Mon, 09 May 2016 07:58:57 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59277) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1azjpu-0002Cr-GK for qemu-devel@nongnu.org; Mon, 09 May 2016 07:58:54 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id EDC868553D; Mon, 9 May 2016 11:58:53 +0000 (UTC) Received: from [10.36.112.65] (ovpn-112-65.ams2.redhat.com [10.36.112.65]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u49Bwmnc027023 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 9 May 2016 07:58:50 -0400 To: Peter Xu , Jan Kiszka References: <1461055122-32378-1-git-send-email-peterx@redhat.com> <571DA823.1030003@web.de> <20160425071806.GF3261@pxdev.xzpeter.org> <571DC61C.9020006@web.de> <20160426073426.GD28545@pxdev.xzpeter.org> From: Paolo Bonzini Message-ID: <57307B78.9030000@redhat.com> Date: Mon, 9 May 2016 13:58:48 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.1 MIME-Version: 1.0 In-Reply-To: <20160426073426.GD28545@pxdev.xzpeter.org> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-devel] [PATCH v4 00/16] IOMMU: Enable interrupt remapping for Intel IOMMU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, mst@redhat.com, jasowang@redhat.com, rkrcmar@redhat.com, qemu-devel@nongnu.org, alex.williamson@redhat.com, wexu@redhat.com, marcel@redhat.com, imammedo@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 26/04/2016 09:34, Peter Xu wrote: > +/* > + * This is to satisfy the hack in Linux kernel. One hack of it is to > + * simulate clearing the Remote IRR bit of IOAPIC entry using the > + * following: > + * > + * "For IO-APIC's with EOI register, we use that to do an explicit EOI. > + * Otherwise, we simulate the EOI message manually by changing the trigger > + * mode to edge and then back to level, with RTE being masked during > + * this." > + * > + * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701) > + * > + * This is based on the assumption that, Remote IRR bit will be > + * cleared by IOAPIC hardware for edge-triggered interrupts (I > + * believe that's what the IOAPIC version 0x1X hardware does). So > + * if we are emulating it, we'd better do it the same here, so that > + * the guest kernel hack will work as well on QEMU. > + * > + * Without this, level-triggered interrupts in IR mode might fail to > + * work correctly. > + */ > +static inline void > +ioapic_fix_edge_remote_irr(uint64_t *entry) > +{ > + if (*entry & IOAPIC_LVT_TRIGGER_MODE) { > + /* Level triggered interrupts, make sure remote IRR is zero */ > + *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR); > + } > +} > + > static void > ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, > unsigned int size) > @@ -314,6 +344,7 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val, > s->ioredtbl[index] &= ~0xffffffffULL; > s->ioredtbl[index] |= val; > } > + ioapic_fix_edge_remote_irr(&s->ioredtbl[index]); > ioapic_service(s); > } > } Is this enough too? Thanks, Paolo diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index 378e663..2443a35 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -72,6 +72,7 @@ static void ioapic_service(IOAPICCommonState *s) (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK; if (trig_mode == IOAPIC_TRIGGER_EDGE) { s->irr &= ~mask; + s->ioredtbl[i] &= ~IOAPIC_LVT_REMOTE_IRR; } else { coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR; s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;