diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h
index 60bbe33..a06e263 100644
--- a/linux-user/ioctls.h
+++ b/linux-user/ioctls.h
@@ -522,4 +522,47 @@
   IOCTL(DRM_IOCTL_I915_GEM_GET_CACHING, IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_i915_gem_caching)))
   IOCTL(DRM_IOCTL_I915_REG_READ, IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_i915_reg_read)))
   IOCTL(DRM_IOCTL_I915_GET_RESET_STATS, IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_i915_reset_stats)))
-  IOCTL(DRM_IOCTL_I915_GEM_USERPTR, IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_i915_gem_userptr)))
\ No newline at end of file
+  IOCTL(DRM_IOCTL_I915_GEM_USERPTR, IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_i915_gem_userptr)))
+
+  IOCTL(DRM_IOCTL_RADEON_CP_INIT    , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_init_t)))
+  IOCTL(DRM_IOCTL_RADEON_CP_START   , 0,  TYPE_NULL)
+  IOCTL(DRM_IOCTL_RADEON_CP_STOP    , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_cp_stop_t)))
+  IOCTL(DRM_IOCTL_RADEON_CP_RESET   , 0,  TYPE_NULL)
+  IOCTL(DRM_IOCTL_RADEON_CP_IDLE    , 0,  TYPE_NULL)
+  IOCTL(DRM_IOCTL_RADEON_RESET      , 0,  TYPE_NULL)
+  IOCTL(DRM_IOCTL_RADEON_FULLSCREEN , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_fullscreen_t)))
+  IOCTL(DRM_IOCTL_RADEON_SWAP       , 0,  TYPE_NULL)
+  IOCTL(DRM_IOCTL_RADEON_CLEAR      , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_clear_t)))
+  IOCTL(DRM_IOCTL_RADEON_VERTEX     , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_vertex_t)))
+  IOCTL(DRM_IOCTL_RADEON_INDICES    , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_indices_t)))
+  IOCTL(DRM_IOCTL_RADEON_STIPPLE    , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_stipple_t)))
+  IOCTL(DRM_IOCTL_RADEON_INDIRECT   , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_indirect_t)))
+  IOCTL(DRM_IOCTL_RADEON_TEXTURE    , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_texture_t)))
+  IOCTL(DRM_IOCTL_RADEON_VERTEX2    , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_vertex2_t)))
+  IOCTL(DRM_IOCTL_RADEON_CMDBUF     , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_cmd_buffer_t)))
+  IOCTL(DRM_IOCTL_RADEON_GETPARAM   , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_getparam_t)))
+  IOCTL(DRM_IOCTL_RADEON_FLIP       , 0,  TYPE_NULL)
+  IOCTL(DRM_IOCTL_RADEON_ALLOC      , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_mem_alloc_t)))
+  IOCTL(DRM_IOCTL_RADEON_FREE       , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_mem_free_t)))
+  IOCTL(DRM_IOCTL_RADEON_INIT_HEAP  , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_mem_init_heap_t)))
+  IOCTL(DRM_IOCTL_RADEON_IRQ_EMIT   , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_irq_emit_t)))
+  IOCTL(DRM_IOCTL_RADEON_IRQ_WAIT   , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_irq_wait_t)))
+  IOCTL(DRM_IOCTL_RADEON_CP_RESUME  , 0,  TYPE_NULL)
+  IOCTL(DRM_IOCTL_RADEON_SETPARAM   , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_setparam_t)))
+  IOCTL(DRM_IOCTL_RADEON_SURF_ALLOC , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_surface_alloc_t)))
+  IOCTL(DRM_IOCTL_RADEON_SURF_FREE  , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_surface_free_t)))
+  IOCTL(DRM_IOCTL_RADEON_GEM_INFO       , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_gem_info)))
+  IOCTL(DRM_IOCTL_RADEON_GEM_CREATE     , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_gem_create)))
+  IOCTL(DRM_IOCTL_RADEON_GEM_MMAP       , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_gem_mmap)))
+  IOCTL(DRM_IOCTL_RADEON_GEM_PREAD      , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_gem_pread)))
+  IOCTL(DRM_IOCTL_RADEON_GEM_PWRITE     , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_gem_pwrite)))
+  IOCTL(DRM_IOCTL_RADEON_GEM_SET_DOMAIN , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_gem_set_domain)))
+  IOCTL(DRM_IOCTL_RADEON_GEM_WAIT_IDLE  , IOC_W,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_gem_wait_idle)))
+  IOCTL(DRM_IOCTL_RADEON_CS             , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_cs)))
+  IOCTL(DRM_IOCTL_RADEON_INFO           , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_info)))
+  IOCTL(DRM_IOCTL_RADEON_GEM_SET_TILING , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_gem_set_tiling)))
+  IOCTL(DRM_IOCTL_RADEON_GEM_GET_TILING , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_gem_get_tiling)))
+  IOCTL(DRM_IOCTL_RADEON_GEM_BUSY       , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_gem_busy)))
+  IOCTL(DRM_IOCTL_RADEON_GEM_VA         , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_gem_va)))
+  IOCTL(DRM_IOCTL_RADEON_GEM_OP         , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_gem_op)))
+  IOCTL(DRM_IOCTL_RADEON_GEM_USERPTR    , IOC_RW,
MK_PTR(MK_STRUCT(STRUCT_drm_radeon_gem_userptr)))
\ No newline at end of file
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 96d285a..602e445 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -84,6 +84,7 @@ int __clone2(int (*fn)(void *), void *child_stack_base,
  #include <libdrm/drm.h>
 #include <libdrm/i915_drm.h>
+#include <libdrm/radeon_drm.h>
 #include <linux/termios.h>
 #include <linux/unistd.h>
 #include <linux/cdrom.h>
@@ -110,6 +111,20 @@ int __clone2(int (*fn)(void *), void *child_stack_base,
 #include "linux_loop.h"
 #include "uname.h"
 +#ifndef DRM_RADEON_GEM_USERPTR
+
+#define DRM_RADEON_GEM_USERPTR          0x2d
+#define DRM_IOCTL_RADEON_GEM_USERPTR    DRM_IOWR(DRM_COMMAND_BASE +
DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)
+
+struct drm_radeon_gem_userptr {
+       uint64_t                addr;
+       uint64_t                size;
+       uint32_t                flags;
+       uint32_t                handle;
+};
+
+#endif
+
 #include "qemu.h"
  #define CLONE_NPTL_FLAGS2 (CLONE_SETTLS | \
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 275583a..23baa15 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -2742,4 +2742,47 @@ struct target_user_cap_data {
 #define TARGET_DRM_IOCTL_I915_GEM_GET_CACHING         TARGET_IOW('d',
0x70, struct drm_i915_gem_caching)
 #define TARGET_DRM_IOCTL_I915_REG_READ                TARGET_IOWR('d',
 0x71, struct drm_i915_reg_read)
 #define TARGET_DRM_IOCTL_I915_GET_RESET_STATS         TARGET_IOWR('d',
 0x72, struct drm_i915_reset_stats)
-#define TARGET_DRM_IOCTL_I915_GEM_USERPTR             TARGET_IOWR('d',
 0x73, struct drm_i915_gem_userptr)
\ No newline at end of file
+#define TARGET_DRM_IOCTL_I915_GEM_USERPTR             TARGET_IOWR('d',
 0x73, struct drm_i915_gem_userptr)
+
+#define TARGET_DRM_IOCTL_RADEON_CP_INIT               TARGET_IOW( 'd',
 0x40, drm_radeon_init_t)
+#define TARGET_DRM_IOCTL_RADEON_CP_START              TARGET_IO(  'd',
 0x41)
+#define TARGET_DRM_IOCTL_RADEON_CP_STOP               TARGET_IOW( 'd',
 0x42, drm_radeon_cp_stop_t)
+#define TARGET_DRM_IOCTL_RADEON_CP_RESET              TARGET_IO(  'd',
 0x43)
+#define TARGET_DRM_IOCTL_RADEON_CP_IDLE               TARGET_IO(  'd',
 0x44)
+#define TARGET_DRM_IOCTL_RADEON_RESET                 TARGET_IO(  'd',
 0x45)
+#define TARGET_DRM_IOCTL_RADEON_FULLSCREEN            TARGET_IOW( 'd',
 0x46, drm_radeon_fullscreen_t)
+#define TARGET_DRM_IOCTL_RADEON_SWAP                  TARGET_IO(  'd',
 0x47)
+#define TARGET_DRM_IOCTL_RADEON_CLEAR                 TARGET_IOW( 'd',
 0x48, drm_radeon_clear_t)
+#define TARGET_DRM_IOCTL_RADEON_VERTEX                TARGET_IOW( 'd',
 0x49, drm_radeon_vertex_t)
+#define TARGET_DRM_IOCTL_RADEON_INDICES               TARGET_IOW( 'd',
 0x4a, drm_radeon_indices_t)
+#define TARGET_DRM_IOCTL_RADEON_STIPPLE               TARGET_IOW( 'd',
 0x4c, drm_radeon_stipple_t)
+#define TARGET_DRM_IOCTL_RADEON_INDIRECT              TARGET_IOWR('d',
 0x4d, drm_radeon_indirect_t)
+#define TARGET_DRM_IOCTL_RADEON_TEXTURE               TARGET_IOWR('d',
 0x4e, drm_radeon_texture_t)
+#define TARGET_DRM_IOCTL_RADEON_VERTEX2               TARGET_IOW( 'd',
 0x4f, drm_radeon_vertex2_t)
+#define TARGET_DRM_IOCTL_RADEON_CMDBUF                TARGET_IOW( 'd',
 0x50, drm_radeon_cmd_buffer_t)
+#define TARGET_DRM_IOCTL_RADEON_GETPARAM              TARGET_IOWR('d',
 0x51, drm_radeon_getparam_t)
+#define TARGET_DRM_IOCTL_RADEON_FLIP                  TARGET_IO(  'd',
 0x52)
+#define TARGET_DRM_IOCTL_RADEON_ALLOC                 TARGET_IOWR('d',
 0x53, drm_radeon_mem_alloc_t)
+#define TARGET_DRM_IOCTL_RADEON_FREE                  TARGET_IOW( 'd',
 0x54, drm_radeon_mem_free_t)
+#define TARGET_DRM_IOCTL_RADEON_INIT_HEAP             TARGET_IOW( 'd',
 0x55, drm_radeon_mem_init_heap_t)
+#define TARGET_DRM_IOCTL_RADEON_IRQ_EMIT              TARGET_IOWR('d',
 0x56, drm_radeon_irq_emit_t)
+#define TARGET_DRM_IOCTL_RADEON_IRQ_WAIT              TARGET_IOW( 'd',
 0x57, drm_radeon_irq_wait_t)
+#define TARGET_DRM_IOCTL_RADEON_CP_RESUME             TARGET_IO(  'd',
 0x58)
+#define TARGET_DRM_IOCTL_RADEON_SETPARAM              TARGET_IOW( 'd',
 0x59, drm_radeon_setparam_t)
+#define TARGET_DRM_IOCTL_RADEON_SURF_ALLOC            TARGET_IOW( 'd',
 0x5a, drm_radeon_surface_alloc_t)
+#define TARGET_DRM_IOCTL_RADEON_SURF_FREE             TARGET_IOW( 'd',
 0x5b, drm_radeon_surface_free_t)
+#define TARGET_DRM_IOCTL_RADEON_GEM_INFO              TARGET_IOWR('d',
 0x5c, struct drm_radeon_gem_info)
+#define TARGET_DRM_IOCTL_RADEON_GEM_CREATE            TARGET_IOWR('d',
 0x5d, struct drm_radeon_gem_create)
+#define TARGET_DRM_IOCTL_RADEON_GEM_MMAP              TARGET_IOWR('d',
 0x5e, struct drm_radeon_gem_mmap)
+#define TARGET_DRM_IOCTL_RADEON_GEM_PREAD             TARGET_IOWR('d',
 0x61, struct drm_radeon_gem_pread)
+#define TARGET_DRM_IOCTL_RADEON_GEM_PWRITE            TARGET_IOWR('d',
 0x62, struct drm_radeon_gem_pwrite)
+#define TARGET_DRM_IOCTL_RADEON_GEM_SET_DOMAIN        TARGET_IOWR('d',
 0x63, struct drm_radeon_gem_set_domain)
+#define TARGET_DRM_IOCTL_RADEON_GEM_WAIT_IDLE         TARGET_IOW( 'd',
 0x64, struct drm_radeon_gem_wait_idle)
+#define TARGET_DRM_IOCTL_RADEON_CS                    TARGET_IOWR('d',
 0x66, struct drm_radeon_cs)
+#define TARGET_DRM_IOCTL_RADEON_INFO                  TARGET_IOWR('d',
 0x67, struct drm_radeon_info)
+#define TARGET_DRM_IOCTL_RADEON_GEM_SET_TILING        TARGET_IOWR('d',
 0x68, struct drm_radeon_gem_set_tiling)
+#define TARGET_DRM_IOCTL_RADEON_GEM_GET_TILING        TARGET_IOWR('d',
 0x69, struct drm_radeon_gem_get_tiling)
+#define TARGET_DRM_IOCTL_RADEON_GEM_BUSY              TARGET_IOWR('d',
 0x6a, struct drm_radeon_gem_busy)
+#define TARGET_DRM_IOCTL_RADEON_GEM_VA                TARGET_IOWR('d',
 0x6b, struct drm_radeon_gem_va)
+#define TARGET_DRM_IOCTL_RADEON_GEM_OP                TARGET_IOWR('d',
 0x6c, struct drm_radeon_gem_op)
+#define TARGET_DRM_IOCTL_RADEON_GEM_USERPTR           TARGET_IOWR('d',
 0x6d, struct drm_radeon_gem_userptr)
\ No newline at end of file
diff --git a/linux-user/syscall_types.h b/linux-user/syscall_types.h
index d33561a..c5c9ada 100644
--- a/linux-user/syscall_types.h
+++ b/linux-user/syscall_types.h
@@ -903,4 +903,211 @@ STRUCT(drm_i915_gem_userptr,
        TYPE_ULONGLONG, /* user_ptr (u64) */
        TYPE_ULONGLONG, /* user_size (u64) */
        TYPE_ULONG, /* flags (u32) */
-       TYPE_ULONG) /* handle (u32) */
\ No newline at end of file
+       TYPE_ULONG) /* handle (u32) */
+
+STRUCT(drm_radeon_init_t,
+        TYPE_INT, /* func (enum) */
+        TYPE_ULONG, /* sarea_priv_offset */
+        TYPE_INT, /* is_pci */
+        TYPE_INT, /* cp_mode */
+        TYPE_INT, /* gart_size */
+        TYPE_INT, /* ring_size */
+        TYPE_INT, /* sec_timeout */
+
+        TYPE_INT, /* fb_bpp */
+        TYPE_INT, /* front_offset */
+        TYPE_INT, /* ront_pitch */
+        TYPE_INT, /* back_offset */
+        TYPE_INT, /* back_pitch */
+        TYPE_INT, /* depth_bpp */
+        TYPE_INT, /* depth_offset */
+        TYPE_INT, /* depth_pitch */
+
+        TYPE_ULONG, /* fb_offset */
+        TYPE_ULONG, /* mmio_offset */
+        TYPE_ULONG, /* ring_offset */
+        TYPE_ULONG, /* ring_rptr_offset */
+        TYPE_ULONG, /* buffers_offset */
+        TYPE_ULONG) /* gart_textures_offset */
+
+STRUCT(drm_radeon_cp_stop_t,
+        TYPE_INT, /* flush */
+        TYPE_INT) /* idle */
+
+STRUCT(drm_radeon_fullscreen_t,
+        TYPE_INT) /* func (enum) */
+
+STRUCT(drm_radeon_clear_t,
+        TYPE_INT, /* flags */
+        TYPE_INT, /* clear_color */
+        TYPE_INT, /* clear_depth */
+        TYPE_INT, /* color_mask */
+        TYPE_INT, /* depth_mask */
+        TYPE_PTRVOID) /* depth_boxes */
+
+STRUCT(drm_radeon_vertex_t,
+        TYPE_INT, /* prim */
+        TYPE_INT, /* idx */
+        TYPE_INT, /* count */
+        TYPE_INT) /* discard */
+
+STRUCT(drm_radeon_indices_t,
+        TYPE_INT, /* prim */
+        TYPE_INT, /* idx */
+        TYPE_INT, /* start */
+        TYPE_INT, /* end */
+        TYPE_INT) /* discard */
+
+STRUCT(drm_radeon_stipple_t,
+        TYPE_PTRVOID) /* mask */
+
+STRUCT(drm_radeon_indirect_t,
+        TYPE_INT, /* idx */
+        TYPE_INT, /* start */
+        TYPE_INT, /* end */
+        TYPE_INT) /* discard */
+
+STRUCT(drm_radeon_texture_t,
+        TYPE_INT, /* offset */
+        TYPE_INT, /* pitch */
+        TYPE_INT, /* format */
+        TYPE_INT, /* width */
+        TYPE_INT, /* height */
+        TYPE_PTRVOID) /* image */
+
+STRUCT(drm_radeon_vertex2_t,
+        TYPE_INT, /* idx */
+        TYPE_INT, /* discard */
+        TYPE_INT, /* nr_states */
+        TYPE_PTRVOID, /* state */
+        TYPE_INT, /* nr_prims */
+        TYPE_PTRVOID) /* prim */
+
+STRUCT(drm_radeon_cmd_buffer_t,
+        TYPE_INT, /* bufsz */
+        TYPE_PTRVOID, /* buf */
+        TYPE_INT, /* nbox */
+        TYPE_PTRVOID) /* boxes */
+
+STRUCT(drm_radeon_getparam_t,
+        TYPE_INT, /* param */
+        TYPE_PTRVOID) /* value */
+
+STRUCT(drm_radeon_mem_alloc_t,
+        TYPE_INT, /* region */
+        TYPE_INT, /* alignment */
+        TYPE_INT, /* size */
+        TYPE_PTRVOID) /* region_offset */
+
+STRUCT(drm_radeon_mem_free_t,
+        TYPE_INT, /* region */
+        TYPE_INT) /* region_offset */
+
+STRUCT(drm_radeon_mem_init_heap_t,
+        TYPE_INT, /* region */
+        TYPE_INT, /* size */
+        TYPE_INT) /* start */
+
+STRUCT(drm_radeon_irq_emit_t,
+        TYPE_PTRVOID) /* irq_seq */
+
+STRUCT(drm_radeon_irq_wait_t,
+        TYPE_INT) /* irq_seq */
+
+STRUCT(drm_radeon_setparam_t,
+        TYPE_INT, /* param */
+        TYPE_ULONGLONG) /* value */
+
+STRUCT(drm_radeon_surface_alloc_t,
+        TYPE_INT, /* address */
+        TYPE_INT, /* size */
+        TYPE_INT) /* flags */
+
+STRUCT(drm_radeon_surface_free_t,
+        TYPE_INT) /* address */
+
+STRUCT(drm_radeon_gem_info,
+        TYPE_ULONGLONG,  /* gart_size */
+        TYPE_ULONGLONG,  /* vram_size */
+        TYPE_ULONGLONG)  /* vram_visible */
+
+STRUCT(drm_radeon_gem_create,
+        TYPE_ULONGLONG,  /* size */
+        TYPE_ULONGLONG,  /* alignment */
+        TYPE_INT,        /* handle */
+        TYPE_INT,        /* initial_domain */
+        TYPE_INT)        /* flags */
+
+STRUCT(drm_radeon_gem_mmap,
+        TYPE_INT,        /* handle */
+        TYPE_INT,        /* pad */
+        TYPE_ULONGLONG,  /* offset */
+        TYPE_ULONGLONG,  /* size */
+        TYPE_ULONGLONG)  /* addr_ptr */
+
+STRUCT(drm_radeon_gem_pread,
+        TYPE_INT,       /* handle */
+        TYPE_INT,       /* pad */
+        TYPE_ULONGLONG, /* offset */
+        TYPE_ULONGLONG, /* size */
+        TYPE_ULONGLONG) /* data_ptr */
+
+STRUCT(drm_radeon_gem_pwrite,
+        TYPE_INT,       /* handle */
+        TYPE_INT,       /* pad */
+        TYPE_ULONGLONG, /* offset */
+        TYPE_ULONGLONG, /* size */
+        TYPE_ULONGLONG) /* data_ptr */
+
+STRUCT(drm_radeon_gem_set_domain,
+        TYPE_INT,        /* handle */
+        TYPE_INT,        /* read_domains */
+        TYPE_INT)        /* write_domain */
+
+STRUCT(drm_radeon_gem_wait_idle,
+        TYPE_INT,        /* handle */
+        TYPE_INT)        /* pad */
+
+STRUCT(drm_radeon_cs,
+        TYPE_INT,        /* num_chunks */
+        TYPE_INT,        /* cs_id */
+        TYPE_ULONGLONG,  /* chunks */
+        TYPE_ULONGLONG,  /* gart_limit */
+        TYPE_ULONGLONG)  /* vram_limit */
+
+STRUCT(drm_radeon_info,
+        TYPE_INT,        /* request */
+        TYPE_INT,        /* pad */
+        TYPE_ULONGLONG)  /* value */
+
+STRUCT(drm_radeon_gem_set_tiling,
+        TYPE_INT,        /* handle */
+        TYPE_INT,        /* tiling_flags */
+        TYPE_INT)        /* pitch */
+
+STRUCT(drm_radeon_gem_get_tiling,
+        TYPE_INT,        /* handle */
+        TYPE_INT,        /* tiling_flags */
+        TYPE_INT)        /* pitch */
+
+STRUCT(drm_radeon_gem_busy,
+        TYPE_INT,        /* handle */
+        TYPE_INT)        /* domain */
+
+STRUCT(drm_radeon_gem_va,
+        TYPE_INT,         /* handle */
+        TYPE_INT,         /* operation */
+        TYPE_INT,         /* vm_id */
+        TYPE_INT,         /* flags */
+        TYPE_ULONGLONG)   /* offset */
+
+STRUCT(drm_radeon_gem_op,
+        TYPE_INT,         /* handle */
+        TYPE_INT,         /* op */
+        TYPE_ULONGLONG)   /* value */
+
+STRUCT(drm_radeon_gem_userptr,
+       TYPE_ULONGLONG,    /* addr */
+       TYPE_ULONGLONG,    /* size */
+       TYPE_INT,          /* flags */
+       TYPE_INT)          /* handle */
\ No newline at end of file
