@@ -1471,7 +1471,7 @@ static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)
break;
return ret;
}
- /* Fall through. */
+ fallthrough;
case 0x000 ... 0x2fe:
reg = addr & 0x3f;
ch = (addr >> 6) & 0x0f;
@@ -1482,7 +1482,7 @@ static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)
case 0x404 ... 0x4fe:
if (s->model <= omap_dma_3_1)
break;
- /* Fall through. */
+ fallthrough;
case 0x400:
if (omap_dma_sys_read(s, addr, &ret))
break;
@@ -1519,7 +1519,7 @@ static void omap_dma_write(void *opaque, hwaddr addr,
break;
return;
}
- /* Fall through. */
+ fallthrough;
case 0x000 ... 0x2fe:
reg = addr & 0x3f;
ch = (addr >> 6) & 0x0f;
@@ -1530,7 +1530,7 @@ static void omap_dma_write(void *opaque, hwaddr addr,
case 0x404 ... 0x4fe:
if (s->model <= omap_dma_3_1)
break;
- /* fall through */
+ fallthrough;
case 0x400:
if (omap_dma_sys_write(s, addr, value))
break;
@@ -1716,25 +1716,25 @@ static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
case 0x14: /* DMA4_IRQSTATUS_L3 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x10: /* DMA4_IRQSTATUS_L2 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x0c: /* DMA4_IRQSTATUS_L1 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x08: /* DMA4_IRQSTATUS_L0 */
return s->irqstat[irqn];
case 0x24: /* DMA4_IRQENABLE_L3 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x20: /* DMA4_IRQENABLE_L2 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x1c: /* DMA4_IRQENABLE_L1 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x18: /* DMA4_IRQENABLE_L0 */
return s->irqen[irqn];
@@ -1870,13 +1870,13 @@ static void omap_dma4_write(void *opaque, hwaddr addr,
switch (addr) {
case 0x14: /* DMA4_IRQSTATUS_L3 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x10: /* DMA4_IRQSTATUS_L2 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x0c: /* DMA4_IRQSTATUS_L1 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x08: /* DMA4_IRQSTATUS_L0 */
s->irqstat[irqn] &= ~value;
if (!s->irqstat[irqn])
@@ -1885,13 +1885,13 @@ static void omap_dma4_write(void *opaque, hwaddr addr,
case 0x24: /* DMA4_IRQENABLE_L3 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x20: /* DMA4_IRQENABLE_L2 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x1c: /* DMA4_IRQENABLE_L1 */
irqn ++;
- /* fall through */
+ fallthrough;
case 0x18: /* DMA4_IRQENABLE_L0 */
s->irqen[irqn] = value;
return;
@@ -278,7 +278,7 @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
switch (offset) {
case DRCMR64 ... DRCMR74:
offset -= DRCMR64 - DRCMR0 - (64 << 2);
- /* Fall through */
+ fallthrough;
case DRCMR0 ... DRCMR63:
channel = (offset - DRCMR0) >> 2;
return s->req[channel];
@@ -338,7 +338,7 @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,
switch (offset) {
case DRCMR64 ... DRCMR74:
offset -= DRCMR64 - DRCMR0 - (64 << 2);
- /* Fall through */
+ fallthrough;
case DRCMR0 ... DRCMR63:
channel = (offset - DRCMR0) >> 2;
@@ -220,7 +220,7 @@ static void dma_mem_write(void *opaque, hwaddr addr,
break;
case 1:
s->dmaregs[0] |= DMA_LOADED;
- /* fall through */
+ fallthrough;
default:
s->dmaregs[saddr] = val;
break;
In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword. Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidianakis@linaro.org> --- hw/dma/omap_dma.c | 32 ++++++++++++++++---------------- hw/dma/pxa2xx_dma.c | 4 ++-- hw/dma/sparc32_dma.c | 2 +- 3 files changed, 19 insertions(+), 19 deletions(-)