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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id o4sm11388151pjo.16.2020.07.20.01.40.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 01:40:05 -0700 (PDT) From: Zong Li To: palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/2] target/riscv/pmp.c: Fix the index offset on RV64 Date: Mon, 20 Jul 2020 16:39:57 +0800 Message-Id: <658e49284fc564d4114307cb559cf23ea3e751fd.1595234208.git.zong.li@sifive.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=zong.li@sifive.com; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 20 Jul 2020 05:44:47 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zong Li Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original implementation, the second parameter of pmp_write_cfg is "reg_index * sizeof(target_ulong)", and we get the the result which is started from 16 if reg_index is 2, but we expect that it should be started from 8. Separate the implementation for RV32 and RV64 respectively. Signed-off-by: Zong Li --- target/riscv/pmp.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 2a2b9f5363..adcdd411e6 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -320,8 +320,13 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, for (i = 0; i < sizeof(target_ulong); i++) { cfg_val = (val >> 8 * i) & 0xff; +#if defined(TARGET_RISCV32) pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i, cfg_val); +#elif defined(TARGET_RISCV64) + pmp_write_cfg(env, ((reg_index >> 1) * sizeof(target_ulong)) + i, + cfg_val); +#endif } } @@ -336,7 +341,11 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) target_ulong val = 0; for (i = 0; i < sizeof(target_ulong); i++) { +#if defined(TARGET_RISCV32) val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i); +#elif defined(TARGET_RISCV64) + val = pmp_read_cfg(env, ((reg_index >> 1) * sizeof(target_ulong)) + i); +#endif cfg_val |= (val << (i * 8)); } trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val);