Message ID | 6cb4f31c9b72af4fb81848c233e1be77d1e0e83c.1591827110.git.alistair.francis@wdc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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11 Jun 2020 06:21:08 +0800 IronPort-SDR: em4gQod2I33wuftNjaByBDw6F0otLSJ83K1BHjnxKG5Eako8NldvC1RhvCbX1v3VmooQmmJDxs hkO5ZPmYwg80NLqLjMEL90vov1OdhoCkc= Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2020 15:10:34 -0700 IronPort-SDR: P6gAm0pnUqwEmpqtCZdhD5DJ+E2EhUL0nCJzbWwK6vFzlwehSZeEr1DwJ4s/ocsFMQbyarnxUA c4fgxITEzR9w== WDCIronportException: Internal Received: from us4qd5p12.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.58.34]) by uls-op-cesaip02.wdc.com with ESMTP; 10 Jun 2020 15:21:08 -0700 From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v6 1/6] riscv/opentitan: Fix the ROM size Date: Wed, 10 Jun 2020 15:12:11 -0700 Message-Id: <6cb4f31c9b72af4fb81848c233e1be77d1e0e83c.1591827110.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <cover.1591827110.git.alistair.francis@wdc.com> References: <cover.1591827110.git.alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=68.232.141.245; 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Series |
RISC-V Add the OpenTitan Machine
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expand
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diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index b4fb836466..6c7359c190 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -30,7 +30,7 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } ibex_memmap[] = { - [IBEX_ROM] = { 0x00008000, 0xc000 }, + [IBEX_ROM] = { 0x00008000, 16 * KiB }, [IBEX_RAM] = { 0x10000000, 0x10000 }, [IBEX_FLASH] = { 0x20000000, 0x80000 }, [IBEX_UART] = { 0x40000000, 0x10000 },
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reported-by: Damien Hedde <damien.hedde@greensocs.com> --- hw/riscv/opentitan.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)