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Mon, 05 Oct 2020 18:51:33 +0000 Received: from abhmp0001.oracle.com (abhmp0001.oracle.com [141.146.116.7]) by aserv0121.oracle.com (8.14.4/8.13.8) with ESMTP id 095IpWB1002008; Mon, 5 Oct 2020 18:51:32 GMT Received: from flaka.hsd1.ca.comcast.net (/67.180.143.163) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Mon, 05 Oct 2020 11:51:32 -0700 From: elena.ufimtseva@oracle.com To: qemu-devel@nongnu.org Subject: [PATCH v10 13/19] multi-process: PCI BAR read/write handling for proxy & remote endpoints Date: Mon, 5 Oct 2020 11:51:01 -0700 Message-Id: <6cd201c76fcd768cd5d560e8d5bc80a3594b833b.1601923020.git.elena.ufimtseva@oracle.com> X-Mailer: git-send-email 2.25.GIT In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9765 signatures=668680 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 suspectscore=1 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2010050136 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9765 signatures=668680 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 malwarescore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=1 phishscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 spamscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2010050136 Received-SPF: pass client-ip=156.151.31.85; envelope-from=elena.ufimtseva@oracle.com; helo=userp2120.oracle.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/05 12:40:53 X-ACL-Warn: Detected OS = Linux 3.1-3.10 [fuzzy] X-Spam_score_int: -50 X-Spam_score: -5.1 X-Spam_bar: ----- X-Spam_report: (-5.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.733, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: elena.ufimtseva@oracle.com, fam@euphon.net, swapnil.ingle@nutanix.com, john.g.johnson@oracle.com, kraxel@redhat.com, jag.raman@oracle.com, quintela@redhat.com, mst@redhat.com, armbru@redhat.com, kanth.ghatraju@oracle.com, felipe@nutanix.com, thuth@redhat.com, ehabkost@redhat.com, konrad.wilk@oracle.com, dgilbert@redhat.com, stefanha@redhat.com, thanos.makatos@nutanix.com, rth@twiddle.net, kwolf@redhat.com, berrange@redhat.com, mreitz@redhat.com, ross.lagerwall@citrix.com, marcandre.lureau@gmail.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Jagannathan Raman Proxy device object implements handler for PCI BAR writes and reads. The handler uses BAR_WRITE/BAR_READ message to communicate to the remote process with the BAR address and value to be written/read. The remote process implements handler for BAR_WRITE/BAR_READ message. Signed-off-by: Jagannathan Raman Signed-off-by: Elena Ufimtseva Signed-off-by: John G Johnson Reviewed-by: Stefan Hajnoczi --- hw/i386/remote-msg.c | 87 ++++++++++++++++++++++++++++++++++++++++ hw/pci/proxy.c | 60 +++++++++++++++++++++++++++ include/hw/pci/proxy.h | 10 +++++ include/io/mpqemu-link.h | 10 +++++ io/mpqemu-link.c | 6 +++ 5 files changed, 173 insertions(+) diff --git a/hw/i386/remote-msg.c b/hw/i386/remote-msg.c index 94937db1c5..9b9ca7ea53 100644 --- a/hw/i386/remote-msg.c +++ b/hw/i386/remote-msg.c @@ -16,11 +16,14 @@ #include "qapi/error.h" #include "sysemu/runstate.h" #include "hw/pci/pci.h" +#include "exec/memattrs.h" static void process_config_write(QIOChannel *ioc, PCIDevice *dev, MPQemuMsg *msg); static void process_config_read(QIOChannel *ioc, PCIDevice *dev, MPQemuMsg *msg); +static void process_bar_write(QIOChannel *ioc, MPQemuMsg *msg, Error **errp); +static void process_bar_read(QIOChannel *ioc, MPQemuMsg *msg, Error **errp); void coroutine_fn mpqemu_remote_msg_loop_co(void *data) { @@ -55,6 +58,12 @@ void coroutine_fn mpqemu_remote_msg_loop_co(void *data) case PCI_CONFIG_READ: process_config_read(com->ioc, pci_dev, &msg); break; + case BAR_WRITE: + process_bar_write(com->ioc, &msg, &local_err); + break; + case BAR_READ: + process_bar_read(com->ioc, &msg, &local_err); + break; default: error_setg(&local_err, "Unknown command (%d) received for device %s (pid=%d)", @@ -122,3 +131,81 @@ static void process_config_read(QIOChannel *ioc, PCIDevice *dev, getpid()); } } + +static void process_bar_write(QIOChannel *ioc, MPQemuMsg *msg, Error **errp) +{ + BarAccessMsg *bar_access = &msg->data.bar_access; + AddressSpace *as = + bar_access->memory ? &address_space_memory : &address_space_io; + MPQemuMsg ret = { 0 }; + MemTxResult res; + uint64_t val; + Error *local_err = NULL; + + if (!is_power_of_2(bar_access->size) || + (bar_access->size > sizeof(uint64_t))) { + ret.data.u64 = UINT64_MAX; + goto fail; + } + + val = cpu_to_le64(bar_access->val); + + res = address_space_rw(as, bar_access->addr, MEMTXATTRS_UNSPECIFIED, + (void *)&val, bar_access->size, true); + + if (res != MEMTX_OK) { + error_setg(errp, "Could not perform address space write operation," + " inaccessible address: %lx in pid %d.", + bar_access->addr, getpid()); + ret.data.u64 = -1; + } + +fail: + ret.cmd = RET_MSG; + ret.size = sizeof(ret.data.u64); + + mpqemu_msg_send(&ret, ioc, &local_err); + if (local_err) { + error_setg(errp, "Error while sending message to proxy " + "in remote process pid=%d", getpid()); + } +} + +static void process_bar_read(QIOChannel *ioc, MPQemuMsg *msg, Error **errp) +{ + BarAccessMsg *bar_access = &msg->data.bar_access; + MPQemuMsg ret = { 0 }; + AddressSpace *as; + MemTxResult res; + uint64_t val = 0; + Error *local_err = NULL; + + as = bar_access->memory ? &address_space_memory : &address_space_io; + + if (!is_power_of_2(bar_access->size) || + (bar_access->size > sizeof(uint64_t))) { + val = UINT64_MAX; + goto fail; + } + + res = address_space_rw(as, bar_access->addr, MEMTXATTRS_UNSPECIFIED, + (void *)&val, bar_access->size, false); + + if (res != MEMTX_OK) { + error_setg(errp, "Could not perform address space read operation," + " inaccessible address: %lx in pid %d.", + bar_access->addr, getpid()); + val = UINT64_MAX; + } + +fail: + ret.cmd = RET_MSG; + ret.data.u64 = le64_to_cpu(val); + ret.size = sizeof(ret.data.u64); + + mpqemu_msg_send(&ret, ioc, &local_err); + if (local_err) { + error_setg(errp, "Error while sending message to proxy " + "in remote process pid=%d", getpid()); + } +} diff --git a/hw/pci/proxy.c b/hw/pci/proxy.c index 083ec8382a..4e23c752cc 100644 --- a/hw/pci/proxy.c +++ b/hw/pci/proxy.c @@ -142,3 +142,63 @@ static void pci_proxy_dev_register_types(void) } type_init(pci_proxy_dev_register_types) + +static void send_bar_access_msg(PCIProxyDev *pdev, MemoryRegion *mr, + bool write, hwaddr addr, uint64_t *val, + unsigned size, bool memory) +{ + MPQemuMsg msg = { 0 }; + long ret = -EINVAL; + Error *local_err = NULL; + + msg.size = sizeof(BarAccessMsg); + msg.data.bar_access.addr = mr->addr + addr; + msg.data.bar_access.size = size; + msg.data.bar_access.memory = memory; + + if (write) { + msg.cmd = BAR_WRITE; + msg.data.bar_access.val = *val; + } else { + msg.cmd = BAR_READ; + } + + ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err); + if (local_err) { + error_report_err(local_err); + } + + if (!write) { + *val = ret; + } +} + +static void proxy_bar_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + ProxyMemoryRegion *pmr = opaque; + + send_bar_access_msg(pmr->dev, &pmr->mr, true, addr, &val, size, + pmr->memory); +} + +static uint64_t proxy_bar_read(void *opaque, hwaddr addr, unsigned size) +{ + ProxyMemoryRegion *pmr = opaque; + uint64_t val; + + send_bar_access_msg(pmr->dev, &pmr->mr, false, addr, &val, size, + pmr->memory); + + return val; +} + +const MemoryRegionOps proxy_mr_ops = { + .read = proxy_bar_read, + .write = proxy_bar_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 8, + }, +}; diff --git a/include/hw/pci/proxy.h b/include/hw/pci/proxy.h index 29b3cdda3e..cc2a3b937e 100644 --- a/include/hw/pci/proxy.h +++ b/include/hw/pci/proxy.h @@ -16,8 +16,17 @@ #define PCI_PROXY_DEV(obj) \ OBJECT_CHECK(PCIProxyDev, (obj), TYPE_PCI_PROXY_DEV) + typedef struct PCIProxyDev PCIProxyDev; +typedef struct ProxyMemoryRegion { + PCIProxyDev *dev; + MemoryRegion mr; + bool memory; + bool present; + uint8_t type; +} ProxyMemoryRegion; + struct PCIProxyDev { PCIDevice parent_dev; char *fd; @@ -31,6 +40,7 @@ struct PCIProxyDev { QemuMutex io_mutex; QIOChannel *ioc; Error *migration_blocker; + ProxyMemoryRegion region[PCI_NUM_REGIONS]; }; #endif /* PROXY_H */ diff --git a/include/io/mpqemu-link.h b/include/io/mpqemu-link.h index 459d345897..234ac82d39 100644 --- a/include/io/mpqemu-link.h +++ b/include/io/mpqemu-link.h @@ -36,6 +36,8 @@ typedef enum { RET_MSG, PCI_CONFIG_WRITE, PCI_CONFIG_READ, + BAR_WRITE, + BAR_READ, MPQEMU_CMD_MAX, } MPQemuCmd; @@ -51,6 +53,13 @@ typedef struct { int l; } ConfDataMsg; +typedef struct { + hwaddr addr; + uint64_t val; + unsigned size; + bool memory; +} BarAccessMsg; + /** * MPQemuMsg: * @cmd: The remote command @@ -70,6 +79,7 @@ typedef struct { uint64_t u64; ConfDataMsg conf_data; SyncSysmemMsg sync_sysmem; + BarAccessMsg bar_access; } data; int fds[REMOTE_MAX_FDS]; diff --git a/io/mpqemu-link.c b/io/mpqemu-link.c index 4e0f57a7f5..44c2875a13 100644 --- a/io/mpqemu-link.c +++ b/io/mpqemu-link.c @@ -277,6 +277,12 @@ bool mpqemu_msg_valid(MPQemuMsg *msg) return false; } break; + case BAR_WRITE: + case BAR_READ: + if ((msg->size != sizeof(BarAccessMsg)) || (msg->num_fds != 0)) { + return false; + } + break; default: break; }