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[85.180.181.74]) by smtp.gmail.com with ESMTPSA id w8sm31242429wmw.4.2017.01.11.12.21.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Jan 2017 12:21:20 -0800 (PST) From: Artyom Tarasenko To: qemu-devel@nongnu.org Date: Wed, 11 Jan 2017 21:19:56 +0100 Message-Id: <6f546cf963e03ed253e16701ba6e30dcc5d00073.1484165352.git.atar4qemu@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c01::241 Subject: [Qemu-devel] [PATCH v2 25/30] target-sparc: implement UA2005 ASI_MMU (0x21) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Artyom Tarasenko --- target/sparc/ldst_helper.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 57b3b97..d34795a 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1394,6 +1394,18 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, ret = env->scratch[i]; break; } + case ASI_MMU: /* UA2005 Context ID registers */ + switch ((addr >> 3) & 0x3) { + case 1: + ret = env->dmmu.mmu_primary_context; + break; + case 2: + ret = env->dmmu.mmu_secondary_context; + break; + default: + cpu_unassigned_access(cs, addr, true, false, 1, size); + } + break; case ASI_DCACHE_DATA: /* D-cache data */ case ASI_DCACHE_TAG: /* D-cache tag access */ case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ @@ -1712,6 +1724,25 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, env->scratch[i] = val; return; } + case ASI_MMU: /* UA2005 Context ID registers */ + { + switch ((addr >> 3) & 0x3) { + case 1: + env->dmmu.mmu_primary_context = val; + env->immu.mmu_primary_context = val; + tlb_flush_by_mmuidx(CPU(cpu), MMU_USER_IDX, MMU_KERNEL_IDX, -1); + break; + case 2: + env->dmmu.mmu_secondary_context = val; + env->immu.mmu_secondary_context = val; + tlb_flush_by_mmuidx(CPU(cpu), MMU_USER_SECONDARY_IDX, + MMU_KERNEL_SECONDARY_IDX, -1); + break; + default: + cpu_unassigned_access(cs, addr, true, false, 1, size); + } + } + return; case ASI_QUEUE: /* UA2005 CPU mondo queue */ case ASI_DCACHE_DATA: /* D-cache data */ case ASI_DCACHE_TAG: /* D-cache tag access */