diff mbox series

[v2,11/11] riscv: sifive_u: Allow up to 4 CPUs to be created

Message ID 71002f073a6e9e611658a19bfe14e00de9790e3b.1550709660.git.alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show
Series Upstream RISC-V fork patches, part 4 | expand

Commit Message

Alistair Francis Feb. 21, 2019, 12:44 a.m. UTC 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7bc25820fe..3199238ba0 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -398,7 +398,10 @@  static void riscv_sifive_u_machine_init(MachineClass *mc)
 {
     mc->desc = "RISC-V Board compatible with SiFive U SDK";
     mc->init = riscv_sifive_u_init;
-    mc->max_cpus = 1;
+    /* The real hardware has 5 CPUs, but one of them is a small embedded power
+     * management CPU.
+     */
+    mc->max_cpus = 4;
 }
 
 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)