From patchwork Sun Sep 11 14:54:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 9325431 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 622B46077F for ; Sun, 11 Sep 2016 14:56:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5372228A01 for ; Sun, 11 Sep 2016 14:56:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4773128A06; Sun, 11 Sep 2016 14:56:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CAFAE28A01 for ; Sun, 11 Sep 2016 14:56:43 +0000 (UTC) Received: from localhost ([::1]:37905 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bj6BX-0005bj-09 for patchwork-qemu-devel@patchwork.kernel.org; Sun, 11 Sep 2016 10:56:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37512) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bj6Au-0005Yo-16 for qemu-devel@nongnu.org; Sun, 11 Sep 2016 10:56:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bj6Ap-0004UW-1N for qemu-devel@nongnu.org; Sun, 11 Sep 2016 10:56:03 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:36653) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bj6Ao-0004UL-SX for qemu-devel@nongnu.org; Sun, 11 Sep 2016 10:55:58 -0400 Received: by mail-pf0-f195.google.com with SMTP id x24so6751885pfa.3 for ; Sun, 11 Sep 2016 07:55:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wPJUMAnG2hhKxZ9V6IBJhquphUvGR4KOfWf5iMCzx0o=; b=hAFxrMTppFZyrN1X4LtQket86Obfbt2cVF/PmzT5jR1qOtMkTkjM8QbJYINdqwGyaQ nKYD0tExDgQiTSF9VwRRuNcqgXIPNCo52FRo/DiT+WorC/i8l7cj+w/jClaN1iX+PpKb U6aKMYQP6hqZ6alMpqgJRmMzTmoyvJsXylDEdQ0lQReZGWwZKAWBCHelT6MW60l+1CFJ 1Wbqh8joXokfZK7lfXi0RthkzsSLmQdt8Bor6OIFtx2IelsWtaCTmXJScKbKWurhR+eG uj6XVW+3ej0mToblqnVUWBlZIO3fN14vfkfoYKgmhVbZynncDyPws4d21fQ281as3Esb UL3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wPJUMAnG2hhKxZ9V6IBJhquphUvGR4KOfWf5iMCzx0o=; b=fUWyLs05JlkpUr2XaDzwNPFCSbXrMnL89hx39bwJ1hlcGyk0gsWIT1X3sEKa6hyC6h kh/Qm39pyBRuGtJFZSGqJynrYslodj9M++CX3ftrEdgj0ZBVV4XTqXMeo6DQDcedcf// 6TEcZlcxzf1JhuR1/JeU2DlVZdfsgh2kOnO/Jva3CvI3f3erB0OoLWZIVCiNviAVzC4Q xWLomnhpnFxuim7rHE/Neu+YExbcPJzrzLMWlKni6u72QhuLDsRugZwPR6qIluBr9uPe 5pkDAMKZC54rJ2m2jqVWCFG5mQKvuxDC/BYW9f3mbJ/CqyDAM+1Cfh35d5+5Odq7yLz7 ZYDw== X-Gm-Message-State: AE9vXwPn5+5liIJB3nCONGO8F1xXgHQy1O7VcJng5DWQAJ/YoC8SxMuEEJ5sxrQ1eP14zA== X-Received: by 10.98.96.193 with SMTP id u184mr24926693pfb.85.1473605698261; Sun, 11 Sep 2016 07:54:58 -0700 (PDT) Received: from localhost ([2601:646:8581:937e:2561:c199:6f8f:8bc8]) by smtp.gmail.com with ESMTPSA id tm1sm18204400pac.23.2016.09.11.07.54.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 11 Sep 2016 07:54:57 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sun, 11 Sep 2016 07:54:57 -0700 Message-Id: <77e182cc5184bdd7618f2ba60f681414cf4a20f3.1473579576.git.alistair@alistair23.me> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.195 Subject: [Qemu-devel] [PATCH v7 7/8] STM32F205: Connect the SPI devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, konstanty@ieee.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Connect the SPI devices to the STM32F205 SoC. Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite --- V2: - Fix up the device/devices commit message hw/arm/stm32f205_soc.c | 22 ++++++++++++++++++++++ include/hw/arm/stm32f205_soc.h | 3 +++ 2 files changed, 25 insertions(+) diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index 20c0754..7162581 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -36,10 +36,13 @@ static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100, 0x40012200 }; +static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800, + 0x40003C00 }; static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50}; static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71}; #define ADC_IRQ 18 +static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51}; static void stm32f205_soc_initfn(Object *obj) { @@ -68,6 +71,12 @@ static void stm32f205_soc_initfn(Object *obj) TYPE_STM32F2XX_ADC); qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default()); } + + for (i = 0; i < STM_NUM_SPIS; i++) { + object_initialize(&s->spi[i], sizeof(s->spi[i]), + TYPE_STM32F2XX_SPI); + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); + } } static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) @@ -168,6 +177,19 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) sysbus_mmio_map(busdev, 0, adc_addr[i]); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, gic_adc_irq_arr[i]); } + + /* SPI 1 and 2 */ + for (i = 0; i < STM_NUM_SPIS; i++) { + dev = DEVICE(&(s->spi[i])); + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, spi_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i])); + } } static Property stm32f205_soc_properties[] = { diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 1adf824..1332141 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -30,6 +30,7 @@ #include "hw/char/stm32f2xx_usart.h" #include "hw/adc/stm32f2xx_adc.h" #include "hw/or-irq.h" +#include "hw/ssi/stm32f2xx_spi.h" #define TYPE_STM32F205_SOC "stm32f205-soc" #define STM32F205_SOC(obj) \ @@ -38,6 +39,7 @@ #define STM_NUM_USARTS 6 #define STM_NUM_TIMERS 4 #define STM_NUM_ADCS 3 +#define STM_NUM_SPIS 3 #define FLASH_BASE_ADDRESS 0x08000000 #define FLASH_SIZE (1024 * 1024) @@ -56,6 +58,7 @@ typedef struct STM32F205State { STM32F2XXUsartState usart[STM_NUM_USARTS]; STM32F2XXTimerState timer[STM_NUM_TIMERS]; STM32F2XXADCState adc[STM_NUM_ADCS]; + STM32F2XXSPIState spi[STM_NUM_SPIS]; qemu_or_irq *adc_irqs; } STM32F205State;