From patchwork Fri May 13 09:46:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 12848615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BAD43C433EF for ; Fri, 13 May 2022 09:58:17 +0000 (UTC) Received: from localhost ([::1]:49784 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1npS3s-0004yH-Mc for qemu-devel@archiver.kernel.org; Fri, 13 May 2022 05:58:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50282) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1npRt6-000706-QD; Fri, 13 May 2022 05:47:09 -0400 Received: from mail-sender.a4lg.com ([153.120.152.154]:53432 helo=mail-sender-0.a4lg.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1npRt4-00053M-Pu; Fri, 13 May 2022 05:47:08 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 904B3300089; Fri, 13 May 2022 09:47:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1652435224; bh=y79/woGSfNLd3iD/cVnXQ2zRaxqr5fVW9oSuusMUpPA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=r+ykMbmkwsSlBKNtE2tI2w0R3swFTb26s1IuebXMIdBaUEKlH5kCe9mfSCb/7l1c0 2m/vqy4GIUXEy5GU+2auK37tgqk96dm0MuifoqBmHN5Q/NxNSg92EOSH3wEEcXMEge Qi/pMrTpIM8g5rB37+NRyOq7JijAWighg+S3IJHU= From: Tsukasa OI To: Tsukasa OI , Alistair Francis , Frank Chang , Dao Lu Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC PATCH 1/1] target/riscv: Make property names lowercase Date: Fri, 13 May 2022 18:46:53 +0900 Message-Id: <794f7476c911de3bc459eb188c181a4119e10997.1652435208.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Received-SPF: pass client-ip=153.120.152.154; envelope-from=research_trasio@irq.a4lg.com; helo=mail-sender-0.a4lg.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Many properties for extension names are just in lowercase. On the other hand, following extension properties and "Counters" are capitalized. - Zifencei - Zicsr - Zfh - Zfhmin - Zve32f - Zve64f This commit chooses lowercase as primary property names but keeps capitalized names as aliases for compatibility. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ccacdee215..16227a1ac5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -822,17 +822,26 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), + DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true), + DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true), + DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false), + DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false), + DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false), + DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), + /* Capitalized aliases */ + DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, qdev_prop_bool, bool), + DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, qdev_prop_bool, bool), + DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool), + DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool), + DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, bool), + DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, bool), + DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, bool), + DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),